[openrisc] nios 2.0 sopc builder's cpu logic and or1k

["=?GB2312?Q?=C7=C7=B3=E7?=" <qcq@mail.ustc.edu.cn>]

    I recently have used altera's nios 2.0's sopc builder.It is a atera's nios cpu fpga core builder used in quartus.
sopc builder can help you build a system in fpga using nios cpu core with support of rom,ram,flash,sdram controller etc. 
when you compile the project,it will generate all verilog files,which include nios cpu core,rom,ram,flash controller,sdram controller and  it will also generate the nios cpu .c .s source files which are library or test codes of the system.
I have take a glimpse of the cpu verilog code and find that it is also a dsp architecture,and cpu is connected with other devices
using crossbar bus connect.so the code fectching  and data  r/w can work at the same time.
If you have time,I think it is worth to read the code.

　　　　　　　　qcq@mail.ustc.edu.cn
　　　　　　　　　　2003-04-16




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