[openrisc] Re: [ECOS] OpenRISC eCos package

[Bart Veer <bartv@ecoscentric.com>]

>>>>> "Robert" == Robert Cragie <rcc@jennic.com> writes:

    Robert> Hi Scott,
    Robert> I am starting to use the OpenRISC eCos package submitted
    Robert> by you for our custom target. As we are not using cache or
    Robert> MMU, this has raised some issues (note I'm not that
    Robert> familiar with the CDL and have some limited experience of
    Robert> porting, so please bear with me).

    Robert> 1) What's the best way to approach configuration for a
    Robert> 'soft' processor like this whose architecture can be
    Robert> configured? My thoughts are that you could either:
    <snip>

The issue of soft cores and eCos has come up before, although not
necessarily on public mailing lists. The ideal solution is actually
option (c): generate key HAL code/configury based on the specific CPU
that is being synthesized. For example, OpenRISC allows you to select
details such as cache size. A tool could take the definition of the
synthesized CPU, extract the details of the cache, and either generate
hal_cache.h or some other file that is #include'd by hal_cache.h.
Similarly the presence of on-chip peripherals like ethernet would
affect the cdl_target definition that controls which device packages
should get pulled in, and also the memory map and interrupt line
assignments.

The original eCos design did envisage tools along these lines, either
allowing users to provide details of a traditional fixed platform
(facilitating porting), or extracting such information from a HDL
file, or a combination. Unfortunately this area was not considered a
priority at the time, and the current implementation of eCos
configuration technology does not yet provide all the functionality
that would be required.

Bart

-- 
Bart Veer                       eCos Configuration Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts
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