Re: [openrisc] code tidyup

["Damjan Lampret" <lampret@opencores.org>]

Matt,

thanks for the info. It seems most tools like Cadence NCsim, Synopsys Design
Compiler, Synplicity Synplify don't have a problem if a declaration is
missing. Anyway I'll add declarations to avoid any warnings.

regards,
Damjan

----- Original Message -----
From: <matt.gillespie@jennic.com>
To: <openrisc@opencores.org>
Sent: Tuesday, July 08, 2003 4:57 AM
Subject: [openrisc] code tidyup


> Are you aware that the or1200_top module has 3 wires not declared.
>
> I know that this is legal but you do list all other single wires.
>
> the missing wires are :
>
> icbiu_cab_ic
> icpu_rty_immu
> dcpu_cycstb_cpu
>
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