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Re: [fpu] FPU operations
Hi,
> I have a question about FP operations performed by
> FPU (I am adding FP
> instructions to OR1K - only single precision at the
> moment).
OK thats fine for now
Anyway
> I'll list some of the operations that would be nice
> to have and I hope
> someone can comment if they are simple enough to be
> supported by FPU.
>
> So basic operations that should be supported are:
>
> - SF add (SF stands for single precision FP)
> - SF sub (should this be done with neg+add
> combination?)
I prefer to have two instructions but in the FPU it
will be mapped to teh same unit with a selection bit
> - SF mul
I think we need div
> - SF compare
compare for equality only?
> - conversion operations (should integer<->SF be done
> by basic FPU or is
> there any other idea? Also don't forget if you want
> DF then we need
> SF<->DF)
>
yes we need it but I think there should be also the
ability to use the rounding method in a seperate
instruction may be?
> Extra operations (desired but not really required
> IMO):
> - SF div
> - SF mac (or you can call it madd. Anyway it would
> be nice to have this
> one. It is easy to implement it if FP Add and Mul
> hardware is separate)
If we are going to define MAC we should have a
seperate block for it
> - SF sqrt
At least not full implementation
> - SF neg (MIPS, SPARC & PPC have it - is it required
> by the standard?)
I do not think it is requeired
> - SF abs (MIPS, SPARC & PPC have it - is it required
> by the standard?)
>
It is not a big problem so lets do it
> Instructions like floating point moves between FP
> registers or
> load/stores to/from FP registers are performed
> directly over FP
> register file (no processing required) so I didin't
> mentioned them
> above (I only listed operations that FP calculation
> hardware should be
> able to do).
>
Yes
> I can list FP instructions of MIPS, SPARC and other
> processor
> architectures if there is interest.
>
> regards,
> Damjan
>
>
Regards
Jamil Khatib
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