RE: [fpu] FPU operations

[Damjan Lampret <damjanlampret@yahoo.com>]

> Here is a rough outline of the FPU IOs as I presume the CPU
> would want to see them:
> 
> INPUT	[31:0]	operand A
> INPUT [31:0]	operand B
> INPUT [3:0]		operation type (TBD, perhaps more bits ?)
> OUTPUT [31:0]	result
> OUTPUT		larger then ( A > B )
> OUTPUT		smaller then (A < B)
> OUTPUT		equal ( A == B )
> OUTPUT		unordered ( A == NAN | B == NAN )
> OUTPUT		overflow
> OUTPUT		underflow
> OUTPUT		SNAN
> OUTPUT		INE
> OUTPUT		INF (not sure we need this)
> 
> Damjan, did I forget something ?
> 
Looks complete to me.

> Regarding pipelining:
> I would suggest that all the basic functions (add, sub, mul and
> divide)
> take the same amount of cycles to execute. I think this will make it
> easier from the CPUs point of view.
> 
Well not really necessary. I took your fmul and replaced mul24 with
carefully balanced 3-stage pipelined multiplier and if I remember
correctly it operated at 400 MHz (complete fmul). I don't know about
fasu but it looks to me that 2-stage piepeline would be enough to be
balanced with fmul. CPU doesn't really care since every insn can take
different number of clk cycles to complete.

> Now, more complex operations (for example square root) might be
> variable
> length execution units, that might signal to the CPU when they are
> done.
> Damjan, can this be done with OR1K ? The CPU would have to monitor
> the
> completion and write the result back out of order. If another
> operation

If number of clk cycles per insn is fixed then it is no problem. If it
depends upon operands then FPU should provide output stall to stall
CPU.

> port for the FPU register file (which I assume is kept inside the

FPU has FP register file which is not the same as integer register
file. This is so that superscalar will be easier to do and also we
don't need so many write ports on current register files.

--damjan


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