Re: [fpu] fdiv

[Rudolf Usselmann <rudi@inet.co.th>]

on 8/20/00 18:22, Jamil Khatib at jamilkhatib75@yahoo.com wrote:
> 
> I think we discussed about the post and pre
> normalization long time ago. I suggest to make the
> post normalization a configurable feature in the core.

Hmm, I believe post normalization should be done by the individual
cores. May be we can combine it later.

> About rounding I thought that there should be a
> seperate block to perform the rounding unless you mean
> teh conversion from the extended format to the single
> one?

I do mean rounding. When you divide 1 by 3 for example,
you need to round properly.
This could probably be a separate block, except then each
core (add/sub, mul, div) will have to provide some additional
bits of the fraction. I think it would be easier for now
to include that function in tot the individual cores as well.
We can always later optimize and combine features.


>> 
>> always @(posedge clk)
>> Q <= #1 D;
> 
> In fact this is the most difficult part of verilog I
> leanred, still I do not know what are the differences
> between #1, = , and <= operators, I think they are
> like signals and variable assignments in VHDL.

'='     this is a blocking assignment. Execution stops until this
        assignment is completed.

'<='    This is a non-blocking assignment. The assignment is
        scheduled, then the execution continues, the actual
        assignment may not have completed yet.

Q <= #1 D   Assigns D to Q. It performs the following steps:
            1) Places the value of D in to a temporary register
            at the time this line is executed.
            2) Schedules to copy the contents of the temporary
            register after 1 time unit in to Q;
            3) After simulation time has advanced to/past 1 time
            unit, the temporary register is assigned to Q.

Basically this simulates the clk -> Q delay, which is important as some
verilog simulators don't behaive correctly.

You are welcome to attend my Verilog class mid October in Bangkok !


> anyhow there are some signals that I want them to be
> assigned at the moment not on teh next simulation time

You should also write a test bench, that will verify that your
block works correctly.


>> There is no need for a reset.
>> 

oops, forgot:
input [1:0]        round_mode;

>> input           clk;
>> input [31:0]    opa, opb;
>> output [31:0]   out;
>> output          div_zero, overflow, underflow,
>> inexact, snan;
>> output          "whatever other exception you can
>> detect";
>> 
> 
> what about teh extended format you used?, in my code I
> am using 32 bit for fraction and 11 bit for exponent

Ahm, there is no extended format. We only do single precision
floating point.

> Sorry for the VHDL like code I am still a beginner

No problem !  Look at my fmul, it's very close to div. It's
also not complete, but will give you a good idea on to code
in verilog.

> Regards
> Jamil Khatib

rudi