Re: [pci] PCI Help

[Damjan Lampret <lampret@opencores.org>]

Hi Hans,

bbeaver@opencores.org is author of behavioral models. However these are
still development version and he probably needs help with verification
of these models.

And at least two other developers are working on PCI synthesizable.
Tadej and Miha will give you more details about PCI synthesizable core.
They need help as well.

regards,
Damjan

"Hans Johansson (ECA)" wrote:
> 
> Hi!
> 
> I have been looking for a good way to simulate a PCI design and then I came across the PCI Core behavioral Master and Target models. This seems to be excactly what I need.
> 
> So I downloaded the files and compiled them with Modelsim.
> However, there seems to be some problems:
> 
> 1. The name of the target model entity referenced by the target architecture is not correct. (Entity is called TG32PCI, but the architecture references an entity called Target32PCI.
> 
> 2. The master command file decoding incorrectly checks for a "WAIT" command, when the actual command is called "CWAT".
> 
> These two errors (in particular nr 1) makes it hard to think that these files have actually been compiled and simulated (the target file won't compile until you change the name "Target32PCI" to TG32PCI.
> Are these really the latest files. If not, how can I get them?
> The CVSWeb states that all files I use are version 1.1.1.1 except the target which is 1.2.
> 
> So I corrected these issues and ran the simulation.
> When doing so, the models report a lot of timing errors (see list below). If these models have been tested with no known errors, shouldn't they run without these kinds of timing errors?
> 
> Maybe I'm doing something wrong here or maybe I don't have the correct files.
> Anyway I need some help with this.
> 
> Also, if I make some useful modifications to the core, I will be happy to share this.
> 
> Thank you,
> 
> Hans Johansson