Re: [pci] PCI bridge project status

["Mihaela & Ovidiu Lupas" <lupasfam@sympatico.ca>]

Hi,

I am interested in the PCI design. I will read the specs and let you know,
but
not before the WE. I am mostly interested in the PCI side ... ;)

I would like a VHDL approach, but Verilog is fine with me, also ...

Best Regards,
Ovidiu



----- Original Message -----
From: Miha Dolenc <mihapci@email.si>
To: <pci@opencores.org>; <cores@opencores.org>
Sent: Thursday, May 03, 2001 7:15 AM
Subject: [pci] PCI bridge project status


> Hello everyone!
>
>    Me and Tadej prepared a bit of PCI bridge core specification(not
complete
> yet) . It's available at:
>
> http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf
>
> Comments, feedback, advices are welcome.
> If anyone would like to help with RTL design, verification or
documentation
> is welcome to post a message on PCI mailing list with information on what
> he/she is interested in regarding PCI bridge project.
>
>
> Regards,
>     Miha Dolenc
>
>