Re: [pci] PCI bridge status

["Ovidiu Lupas" <olupas@opencores.org>]

Hi all !

I am interested in working on the PCI target interface.

Best regards,
   Ovidiu


----- Original Message -----
From: Miha Dolenc <mihapci@email.si>
To: <pci@opencores.org>
Cc: <cores@opencores.org>
Sent: Tuesday, May 08, 2001 10:17 AM
Subject: [pci] PCI bridge status


> Hello all!
>
>     I have updated the specification with some waveforms so it became more
> readable. We have also shrunken it to "only" 1.6MB.
>
> It can still be found on OpenCores CVS on address
> http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf
>
> Now I think there is quite enough information about PCI bridge core
> functionality for us to start working on RTL design ;-) (in Verilog if
> possible). I will think over how tasks can be divided. If anyone has any
> idea about the task that must be done and he/she is interested in doing
it,
> please notify other members of PCI team through this mailing list, so we
> don't do same things twice.
>
> I would like to do WISHBONE slave interface if nobody else is interested
in
> that.
>
> Have fun,
>     Miha Dolenc
>