[pci] Fw: PCI bridge status

["Miha Dolenc" <mihad@opencores.org>]

Hello,
    this is the conversation on pci bridge core between me an bbeaver, if
anyone is interested.

Regards,
    Miha Dolenc


----- Original Message -----
From: <bbeaver@opencores.org>
To: "Miha Dolenc" <mihaPCI@email.si>
Sent: Wednesday, May 09, 2001 11:35 AM
Subject: Re: PCI bridge status


> I tried to mail to the mailing list, but it bounced.
>
> I am working on a PCI Host Bridge too.
>
> I would regret if we ended up with three of them.  But I have to
> admit that I am too busy to finish mine i the next month.
>
> I would like to suggest that you and I (and Tadej?)  might
> talk about the interface the PCI interface will present to the
> host.  Your manual is quite impressive (almost scary), and
> I would like to benefit from your skills.
>
> I have used the Insilicon PCI controller, and it has terrible problems.
> After thinking about things for a long time, I think my started verilog
> PCI interface has a good, solid host interface.  It will allow a user
> to correctly implement the PCI ordering rules with 1 delayed read,
> and I believe this will be the FIRST one around to make the claim.
>
> I will be unavailable all next week.  I can only talk a little this week.
>
> Please, if you want, take a look at pci_blue_constants.vh.
>
> I have 3 FIFOs.
>
> The first FIFO is a Request FIFO, which the Host uses to initiate PCI
> activity.
> It has a 3-bit Type field.
>
> The Second FIFO is a Response FIFO.  Data from Host requests flows
> across this FIFO.  It has a 4-bit Type Field.
>
> This FIFO ALSO carries PCI requests, initiated by an external PCI master.
> This double-use of the FIFO forces the core to implement the ordering
rules.
>
> The Third FIFO is used to send Memory data to the external PCI Master.
>
> This activity CANNOT share the Request FIFO, because then it would
> be necessary for FIFO entries to hop over one-another in order to
> meet the ordering rules.
>
> I will finish this.  It is mostly in my head now.  If you want, you could
> look
> at the type entries, and see if they would influence you in any way.  I
> would
> be DELIGHTED if they ended up in your core, or in your manual.
>
> Got to go now.  I will read mail maybe once or twice more before the
> weekend, then I am off for a week.  Then, back.  If things go well at
> work, I will FINALLY get to write some verilog at last.
>
> Pleased to meet you!
>
> Lawrence
>
>
> -----Original Message-----
> From: Miha Dolenc <mihapci@email.si>
> To: bbeaver@opencores.org <bbeaver@opencores.org>
> Date: Tuesday, May 08, 2001 10:25 AM
> Subject: Fw: PCI bridge status
>
>
> >Hi!
> >
> >    I'm Miha and Damjan pointed me to you regarding PCI bridge core. I
saw
> >that your e-mail is not a part of pci mailing list, so I took a liberty
to
> >send you my last post. I thought you might be interested. Let me know if
> you
> >are. Or better yet, subscribe to PCI mailing list if you like ( it's not
> >that busy ) and let others know what you are interested in also.
> >
> >Thanks for your time,
> >    Miha Dolenc
> >
> >
> >----- Original Message -----
> >From: "Miha Dolenc" <mihapci@email.si>
> >To: <pci@opencores.org>
> >Cc: <cores@opencores.org>
> >Sent: Tuesday, May 08, 2001 7:17 PM
> >Subject: PCI bridge status
> >
> >
> >> Hello all!
> >>
> >>     I have updated the specification with some waveforms so it became
> more
> >> readable. We have also shrunken it to "only" 1.6MB.
> >>
> >> It can still be found on OpenCores CVS on address
> >>
> http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf
> >>
> >> Now I think there is quite enough information about PCI bridge core
> >> functionality for us to start working on RTL design ;-) (in Verilog if
> >> possible). I will think over how tasks can be divided. If anyone has
any
> >> idea about the task that must be done and he/she is interested in doing
> >it,
> >> please notify other members of PCI team through this mailing list, so
we
> >> don't do same things twice.
> >>
> >> I would like to do WISHBONE slave interface if nobody else is
interested
> >in
> >> that.
> >>
> >> Have fun,
> >>     Miha Dolenc
> >>
> >
>