Re: [pci] PCI IP core

["Tadej" <tadej@opencores.org>]

Hi

Thanks for the dead link information. I put it away.

Regarding the questions, I will first answer on the second one, why
is the count (of the "images") limited from 2 to 5 instead of 1 to 6.
    The maximum number of all "images", as you also mentioned, is 6.
Of course you may use none of them or one or all six, but we (I guess
we wasn't so clear about this) were thinking, what should this PCI
core, we are trying to make, have. 1 image is used to access Device
Specific Configuration registers. So there are only 5 images left (that
is why 2 to 5). By default, the PCI core should have (it can also be
changed) 2 images, but the number is also adjustable to the max of 5.

If you don't like this, we can change it, but it is just the matter of
parameters, when synthesizing the core.

And the question, why is address mapping called "image".
    First, if you think (or you know), that address map can not be
called image, we will change it (we are not native speakers and also
Tundra uses this expression in theirs specs). Now I will try to explain,
how were we thinking. If you see one address space on one bus also
on the another bus with different (or even the same) base address, it
is like an image of an address space.

Thanks for qouestions and any suggestions.

Regards, Tadej.

----- Original Message -----
From: <oliver.amft@ch.abb.com>
To: <pci@opencores.org>
Cc: <tadej@opencores.org>
Sent: Friday, May 18, 2001 12:03 PM
Subject: [pci] Fw: PCI IP core


>
>
>
> Well, I'm about to step through the core spec in more detail (just got the
new
> revision). I think this will be a good point to start.
>
> Regarding the web page:
> - I've found some dead link at
> http://www.opencores.org/cores/pci/pci_links.shtml called "Synthesizable
PCI
> core and PCI model written in VHDL" refering to
> http://www.tkt.cs.tut.fi/~havu/pci/models.html.
> This page appears to be removed.
>
> Questions regarding the PCI Core spec (so far):
> - The term "image" probably refers to PCI address maps (to Wishbone). So
the
> question is: Why it is called image and more important why is the count
limited
> from 2 to 5 instead of 1 to 6. (Maybe I've to read the Wishbone spec
first?)
>
> Cheers,
>
> Oliver
>
>
>
>
> > Hi, Oliver!
> >
> > I just updated the PCI web on opencores. It would be nice,
> > if you can comment web page and also the last PCI spec
> > revision.
> > We (Miha and I) tried to explain how we thought about
> > PCI core and its subparts.
> >
> > Any experiences, you can share, would be appreciated.
> >
> > Best regards, Tadej.
> >
> > ----- Original Message -----
> > From: "Oliver Amft" <oam@gmx.net>
> > To: <mihad@opencores.org>
> > Cc: <tadej@opencores.org>
> > Sent: Thursday, May 17, 2001 9:17 AM
> > Subject: PCI IP core
> >
> >
> > > Miha
> > >
> > > I've seen your second posting in comp.arch.fpga regarding the PCI core
> > > development. As I'm quite interested in the open/free core development
I
> > > would like to contribute in VHDL/Verilog design and/or advisory.
> > > Background: I've about 5 years of experience in VHDL design and 2
years
> > > with PCI, including a soft-processor based PCI regression test
> > > environment for an ASIC development, FPGA designs including a
> > > proprietary PCI core (Xilinx) and PCB PCI bus design (FPGAs,
> > > Processors). Currently I'm doing a lot of VHDL consulting and design
> > > advisory. Apart from some lines I've never done Verilog so far (might
> > > become some new challenge, if necessary).
> > > In the meantime I took some secounds to skip through the spec...that's
> > > all so far. Maybe you can provide me with some greater detail of the
> > > project and your working areas.
> > >
> > > Cheers,
> > >
> > > Oliver
> > >
> > > --
> > > GMX - Die Kommunikationsplattform im Internet.
> > > http://www.gmx.net
> > >
> > >
> >
>
>
>