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Re: [pci] FIFO
Hi Oliver, all,
The path to the VHDL simulation files for the PCI
master - target protocol is :
http://www.opencores.org/cvsweb.shtml/pci_core/vhdl_behav/
I am modifying the webpage, too ... Sorry for the inconvenience ...
If you want, I will send you the package in an e-mail. I still have
some problems with the master design, that I might need to rewrite
some pieces of it. Funny thing that it didn't gave any problems in
ActiveVHDL,
as I remember ... Anyway, I hope to clear all the problems in it until
Monday.
Oliver, if you like, you can start working on the PCI master. I said that I
will do it,
because I enjoy doing it and anticipate much fun in the process ... ;) But
this does
not prevent anybody else to give it a try. It is not my property, after all
... ;)
Best regards,
Ovidiu