RE: [pci] burst data phase.

["Tadej" <tadej@opencores.org>]

Hi all!


We made a PCI to WB bridge. So if someone needs any help, two documents are
available on:
http://www.opencores.org/projects/pci/
PCI IP Core Specification & PCI IP Core Design document.

I think that anybody doing PCI bridge or interface should know which
operations of PCI device, he or she wants to make,  MUST be supported and
which are optional.
The best thing would be to read the PCI specification 2.x (from PCI-SIG).


regards,
	Tadej


-----Original Message-----
From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf
Of Adam Xia
Sent: Thursday, February 07, 2002 3:03 PM
To: 'pci@opencores.org'
Subject: RE: [pci] burst data phase.


Hi,
You need a counter to indicate the size of each burst. It is nice to have
hardware retry in case the burst is aborted by other transaction.

Regards,

Adam

-----Original Message-----
From: Pavan [mailto:pavankumar@mistralsoftware.com]
Sent: Wednesday, February 06, 2002 11:51 PM
To: pci@opencores.org
Subject: Re: [pci] burst data phase.


Hi,
In single data phase each word of data is sent and the cycle is terminated.
So the cycle start with FRAME and ends with STOP for each word. But in case
of burst mode the successive words of data are sent in the succesive clocks
. The cycle starts with FRAME and datas are sent continously with each clock
and terminated with STOP signal.

Regards,
Pavan Kumar
----- Original Message -----
From: "rama mohan" <ramu_pci@hotmail.com>
To: <pci@opencores.org>
Sent: Thursday, February 07, 2002 7:29 AM
Subject: Re: [pci] burst data phase.


hay runner,
     Thanks for ur response. What u told i did same thing. My question is
when i want to implement burst data transfer. what i have to do extra logic
than when we develop single data phase transactions.

Thanks once again.

All kinds of suggestions are appreciated.

Thanks
Ramu


>From: runner <runner@zh.t2-design.com>
>Reply-To: pci@opencores.org
>To: "pci@opencores.org" <pci@opencores.org>
>Subject: Re: [pci] burst data phase.
>Date: Thu, 7 Feb 2002 8:45:21 +0800
>
>rama mohan£¬
> the master needn't to know how mang cycles to maintain. in single date
>transfer mode, the FRAME#(driven by master) will maintain active until the
>target asserts the TARRDY# or STOP#. That's to say FRAME# is driven active
>when master need to get/receive data and deasserted when it finishes the
>data phase.
>
>
>
> >pci gurus,
> >       I have devoleped pci 32 bit 33 mhz core with single data phase
> >transaction facility only. I would like to add the burst data phases
> >feature. I am devoleping that. But i strucked at one point.
> >How master come to know that for how many clock cycles to maintain frame.
> >Any body can give me suggestions.
> >All kinds of suggestions are appreciated.
> >
> >thanks in advance
> >
> >ramu
> >
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>             runner@zh.t2-design.com
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