[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: Re: [pci] about turnaround
> full of thanks for giving so detailed description. but i am still wondering who is responsible for keeping shared signals(AD or CBE) stable on PCI bus during turnaround cycle?
Uhm. If the signals had been kept stable, there would not be a
turn-around cycle. The whole point is for the previous driver to
have time to stop driving the signals so that there is no collision
once the new one starts driving.
> i think since the bus is normally driven most of the time, the precharged bus will retain its state for some time. but if it is right, how long the state can be retained.
The PCI bus is not precharged. Some signals have pull-ups, but
that does not include AD[31:0] or C/BE#[3:0].
It is a clocked bus, and values are supposed to be registered on
positive clock flanks. The required hold time is 0 ns, so you
can't expet signals to hold their values at all after the flank
occurs.
--
Chalmers University | Why are these | e-mail: rand@cd.chalmers.se
of Technology | .signatures | johank@omicron.se
| so hard to do | WWW: rand.thn.htu.se
Gothenburg, Sweden | well? | (fVDI, MGIFv5, QLem)
--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml