Re: [pci] question on PCI master

[wilton@mail.usa.com]

Hi Sumnow,

Thanks your kind help but I still get confused. What is the northbridge 
and MMU? and would you pls help to clarify the following:
My understanding is that many PCI masters may exist on a PCI bus. Let 
say there is a Data acquisition chip with PCI master capability. When its 
internal FIFO approaches full, it will generate a interrupt request. Once 
it is granted, it should assert the REQ and begins to transfer data from 
its own FIFO to the system memory after GNT asserted. It seems to me 
that the transfer from DAQ's internal FIFO to system memory needn't 
the CPU to take part in. 
Am I right? If it is the case, how the DAQ -- the PCI initiator, know the 
destination address? Is there any DMA controller devide on the PCI bus?

Best Regards

Wilton

----- Original Message ----- 
From: sumnow <sumnow@2... > 
To: "pci@o... " <pci@o... > 
Date: Sat, 30 Mar 2002 11:52:3 +0800 
Subject: Re: [pci] question on PCI master 

> 
> 
> this is system specific. let me show you an example: 
> 
> there is a pci master in northbridge in intel pci system. when 
> software want to write 0xABCD to a pci device's memory or register 
> such as a video card's video memory. suppose the destination 
> address is 0x12345678. software uses instructions 
>   mov eax, 0x12345678 
>   mov ebx, 0xABCD 
>   mov [eax], ebx 
> 
> when cpu executes the last instruction, it sends address 0x12345678 
> to MMU, MMU knows this address belongs to PCI system so redirects 
> it to northbridge. pci master in northbridge will initiate a pci 
> transaction on pci bus with address 0x12345678 and video card knows 
> this is its own space and will assert DEVSEL# to response. 
> 
> in addition, northbridge can do address remapping if neccessary. 
> 
> in risc machine on which my work is based now, the instructions 
> accessing pci device is LOAD/STORE. 
> 
> i hope this helps. 
> 
> sumnow 
> 
> >Hi! 
> > 
> >COuld anyone here tell me how the PCI master know what is the 
> >destination address when it want to initiate a write transfer? 
> It seems 
> >that the specification doesn't specify how to get the address. 
> > 
> >Awaiting your reply 
> >with regards 
> > 
> >Wilton 
> > 
> >. 
> 
--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml