Re: [pci] about DAC

["Miha Dolenc" <mihad@opencores.org>]

This command is not supported by the bridge. But because the bridge is
capable of generating SERR errors, than the parity checking mechanism must
be able to generate SERR on both phases of dual address cycle to comply with
PCI specification.

Regards,
Miha Dolenc

----- Original Message -----
From: <random_user@163.com>
To: <pci@opencores.org>
Sent: Tuesday, May 28, 2002 6:30 PM
Subject: RE: [pci] about DAC


> When I read pci_parity_check.v,I found :
>
> always@(posedge reset_in or posedge clk_in)
> begin
>     if ( reset_in )
>         check_for_serr_on_second <= #`FF_DELAY 1'b0 ;
>     else
>         check_for_serr_on_second <= #`FF_DELAY
> check_for_serr_on_first && ( pci_cbe_reg_in == `BC_DUAL_ADDR_CYC ) ;
>
*****************
> end
>
> What I mean is the command supported here,dual address command.But
> now I don't want it to be supported.
>
> Thank you very much for your kind help and eager for your reply!
>
> ----- Original Message -----
> From: "Tadej" <tadej@o... >
> To: <pci@o... >
> Date: Tue, 28 May 2002 17:01:24 +0200
> Subject: RE: [pci] about DAC
>
> >
> >
> > Hi
> >
> > What do you mean?
> > PCI cor (bridge) does not have any DAC, except
> > if you have meant the DAC for our application
> > example. This DAC is connected to the CRT (like
> > a VGA core).
> >
> > Regards,
> > Tadej
> >
> > -----Original Message-----
> > From: owner-pci@o...
> > [/cgi-bin/post.cgi?cmd=new&to=owner-pci%20at%20opencores%
> 20dot%20org&msg=/ml-archive/pci/msg00035.shtml
> > Behalf
> > Of random_user@1...
> > Sent: Tuesday, May 28, 2002 4:42 AM
> > To: pci@o...
> > Subject: [pci] about DAC
> >
> >
> > hi all,
> >      If I don't want the DAC to be supported,how many modules
> > should
> > be modified and what are they?
> >
> > regards,
> > wangc
> >
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>


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