RE: [pci] MSI question

["Charles Krinke" <ckrinke@pulselink.net>]

Dear Taeweon:
	A PCI bus allows a number of different commands to be generated by any
device capable of becoming a bus master. The normal action is that a device
requests the use of the bus by asserting its REQ line and the bus is granted
by the system controller by the assertion of GNT by the arbiter. All PCI
slots have an individual REQ/GNT pair that allows any PCI device to assert
REQ (if it has bus master capabilities, which the PCI_BRIDGE32 does).
	Once a device has been granted the bus, it can perform a configuration
read/write, memory read/write or IO read/write. What you might want to study
is the PCI bus commands and how a read/write actually work. It is described
in numerous places on the internet and should be findable without too much
trouble.

Charles

-----Original Message-----
From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf
Of suhtw@ece.gatech.edu
Sent: Tuesday, November 12, 2002 6:03 PM
To: pci@opencores.org
Subject: [pci] MSI question


Hi,

I am a grad student in Georgia Tech. While I was reading a book, PCI
System Architecture, I came up with a question. It's about MSI
(Message Signaled Interrupt).

Book says in p255, PCI System Architecture, when the device must
generate an interrupt request, it writes the Message Data register
contents to the memory address specified in its Message Address
register.

I wonder how possibly the device, I think it's one of target devices, can
initiate a write transaction to PCI bus ?

I would appreciate it if you answer the question.
Thank you

Taeweon
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