[pci] are there any statements in VHDL which can be used to access signals in sub entity

[wuyunsheng <wuyunsheng@mprc.pku.edu.cn>]

to monitor the pci bus, we must use signals in submodule. in verilog we can do this as follows(taken from system.v):

wire devsel_t_s_oe = `PCI_BRIDGE_INSTANCE.DEVSEL_en && `PCI_BRIDGE_INSTANCE.TRDY_en && `PCI_BRIDGE_INSTANCE.STOP_en ;

i wonder if there are any similar statements in VHDL which can be used to access signals in sub entity.

Regards.

            wuyunsheng
            wuyunsheng@mprc.pku.edu.cn

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