[pci] Data Corruption writing into Target

[lnds@hotmail.com]

I'm seeing some data corruption when writing from a fast master into
my slow opencores target (20Mhz wishbone clock, multicycles to process
data).

I'm doing transfers in chunks of 400 words, not bursting, and I see on
average one word corrupted out of these 400 words.  The corrupted word
appears to be scattered randomly, and all data before and after this
word is correct.

After playing around with the base address I've found that the upper
bits of the corrupted data word match and change as the base address
changes, so I'm convinced that the corrupted data word is in fact a
PCI address coming out of the wishbone data port, instead of the real
data.

Slowing down the master to be slower than the slave seems to
completely eliminate the problem.

Miha wrote previously that "A bug was found in PCI Target path of the
bridge in case when external PCI master was able to produce a lot more
data than WISHBONE slave connected to the bridge could sink."

Are there still believed to be problems here, is this a symptom of the
same problem, or other sync problems in the FIFOs?

Thanks,
Ludi.
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