Re: [usb] host controller transceiver?

["Amey Hegde" <amey@controlnet.co.in>]

There is no problem in implementing it on FPGA. 
Are u going in for a 8bit(60MHz) or a 16 bit (30MHz) interface for the 
EHCI ? If u r planning a 8 bit interface then please check if the 
timings are meeting early in the development phase..
-amey 

----- Original Message -----
From: Jecel Assumpcao Jr <jecel@merlintec.com>
Date: Friday, December 28, 2001 10:46 pm
Subject: Re: [usb] host controller transceiver?

> On Wednesday 26 December 2001 22:51, Amey Hegde wrote:
> > but is your usb 2.0 host going to be implemented on FPGA alone? No
> > ASIC implementation?
> 
> That is the idea. Is there a problem that I have overlooked? The 
> processor and memory controller are in the FPGA too, so it seemed 
> like 
> a good idea:
> 
>  http://www.merlintec.com/merlin6/e_main.html
> 
> I'd like to thank Thierry Leroux for his great overview of the 
> available PHY chips. I had looked a several starting from the list 
> http://www.usb.org/developers/data/usb20/bb_vendor_6_01.pdf but 
> your 
> information was more interesting.
> 
> I didn't find anything about the TI part mentioned on this list in 
> their web site. Since Xilinx now has a USB 2 to SCSI kit using the 
> KLSI 
> part, I also looked at it with interest and it was only then that 
> I 
> noticed the missing LS problem.
> 
> -- Jecel
> --
> To unsubscribe from usb mailing list please visit 
> http://www.opencores.org/mailinglists.shtml

--
To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml