Re: [video] About DCT cores

[Richard Herveille <richard@asics.ws>]

You are right, there is limited information available for those cores.
First of all, you can try to understand the testbench, it includes a number of 
real life datasamples.

The data is fed the the core as follows:
cycle1: dstrb asserted (1 cycle only)
cycle2-64: data samples (0-62)
cycle65: data sample(63) dstrb asserted (next sample block)

A datasample block is an 8x8 matrix in the following format
(0,0)(0,1)...(0,6)(0,7)
(1,0)(1,1)...(1,6)(1,7)
.
.
(6,0)(6,1)...(6,6)(6,7)
(7,0)(7,1)...(7,6)(7,7)

The samples are fed sequentually from top to bottom to the core.
Thus data-in: 
(0,0)(0,1)..(0,6)(0,7)(1,0)..(1,7)(2,0)..(2,7)(3,0)..(6,7)(7,0)...(7,7)

dstrb is asserted the cycle before (0,0).
The core is fully pipelined, a new sample can be calculated every clock cycle. 
Immediately after the first block is calculated, a second block can be 
calculated; dstb is asserted the cycle before (0,0), so while the datasample 
(7,7) from the previous block is send to the core.

(x, x)(0,0)...(7,7)(0,0)
dstrb         dstrb

Richard


> > Whereas the DCT unit from the video_compression_systems is a true
> > two-dimensional 8x8 DCT as needed by MPEG.
>
> Hi Richard,
>
> Can you provide input and output data format of DCT used in
> video_compression_systems?
> It's few information about that.
>
> Best Regards,
> Jiang

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