Re: [openrisc] Cell not translated

[psandeep@asu.edu]

Hello,
      I was having similar problem as Lei. I am using Xilinx ISE for 
synthesizing. I have deleted the code in the files that Damjan was 
mentioning, wherein the blocks of Non-Xilinx RAM are coded up. Now 
only Xilinx related RAM blocks are existing, all the rest are deleted. Is 
this approach correct? The code is synthesizing properly now, but I am 
concerned that there is a shorter way.

Regards,
Sandeep.

----- Original Message ----- 
From: "Damjan Lampret" <lampret@o... > 
To: <openrisc@o... > 
Date: Sat, 15 Feb 2003 21:44:13 +0100 
Subject: Re: [openrisc] Cell not translated 

> Heya ! 
> 
> Look at or1200_defines.v, comment out Xilinx and enable your ASIC 
> library vendor. If you ASIc libraries are not (yet) supported, add 
> support for your libraries in all the or1200*spram*.v and 
> or1200*dpram*.v. 
> 
> regards, 
> Damjan 
> 
> ----- Original Message ----- 
> From: LuoLei2000 
> To: openrisc@o...  
> Sent: Friday, February 14, 2003 9:11 PM 
> Subject: [openrisc] Cell not translated 
> 
> Hi, All, 
> 
> I want to use OpenRisc as the netlist for my project. When I try to 
> compile and synthsis, there is warning: 
> Warning: Cell 
> 'or1200_immu_top/or1200_immu_tlb/itlb_mr_ram/ramb4_s16_0' 
> (RAMB4_S16) not translated. (TRANS-1) 
> Warning: Cell 
> 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_0' 
> (RAMB4_S16_1) not translated. (TRANS-1) 
> Warning: Cell 
> 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_1' 
> (RAMB4_S16_param_1) not translated. (TRANS-1) 
> Warning: Cell 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_0' 
> (RAMB4_S4) not translated. (TRANS-1) 
> Warning: Cell 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_1' 
> (RAMB4_S4_param_1) not translated. (TRANS-1) 
> Warning: Cell 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_2' 
> (RAMB4_S4_param_2) not translated. 
> ..... 
> 
> Anyone can tell me why and how to make it synthsizable? 
> 
> Is OpenRisc1200 synthsizable? 
> 
> Thanks in advance. 
> 
> Lei 
> 
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