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Re: [usb] IP Core vs. USB chip...
Thank you for the lesson. That clears up several of my confusions.
Our case is the one you describe as wanting to fit the entire design on a
single FPGA. (or at least as close as we can get)
I"m inclined to go with the 1.1 all-in-the-FPGA solution for the time
Have you or anyone you know of ported your 1.1 USB OC to an Altera
Nios platform? It would be nice to make it SOPC compliant and work
directly with the Avalon switching fabric.
Perhaps we could do (or support) the work and donate it back to the
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
Date: 15 Aug 2003 12:11:10 +0700
Subject: Re: [usb] IP Core vs. USB chip...
> On Fri, 2003-08-15 at 03:57, kland@n... wrote:
> > We're working on an update to an existing USB design based on
> > NetChip chip.
> > I want to consider using a licensed USB 2.0 IP Core (Asic.ws'
> > but I'm unclear on the benefits of going this route.
> > I understand the benefits of much of the logic being easily
> updated by
> > downloading a new version to the FPGA etc.
> > But I don't see the financial benefits. The IP Cores I've
> read about all
> > require a PHY chip that takes up about as much board space and
> > as a dedicated USB chip. (it was posted that USB OC used an
> > PHY which happens to have the exact same number of pins/balls
> as the
> > Agere USB chip)
> > Then there is the normal $15k-$20k startup license fee, which
> > suppose the OC doesn't incur. You need a lot more unit volume
> > we have if the $8-$10 difference between a PHY and full USB
> chip is
> > going to pay off.
> you are absolutely right, using an IP core in an FPGA is
> not always a financial advantage. In fact it might be in
> some cases a more expensive solution than a of-the-shelf
> However, there are application where an IP core does make
> sense. Not everybody is using FPGAs, some people make custom
> chips, in high volume.
> Others are trying to put their entire design (including one
> of the OpenCores IPs) in to a single FPGA and there is no
> of the shelf solution for their needs.
> The USB 1.1 IP core only requires a transceiver. If you do
> need USB 2.0, than you must use an external PHY. Thats because
> USB 2.0 bit clock is running at 480MHz. The receiving end
> requires custom clock recovery, syncing and other high speed
> functions. These are impossible to implement in todays FPGAs.
> > I am wondering if there are any USB IP Cores that require only
> a USB
> > transceiver external to the FPGA? So basically only 4 pins
> and traces
> > would be required.
> > Thank you for any info.
> > Ken
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