GNS is a hierarchical recognition tool for digital and mixed-signal circuits. Starting from a flat transistor level circuit description, the tool identifies the hierarchical structure within the circuit based on user-defined generic recognition rules. The recognition rules are written in a subset of structural VHDL. The genericity of the rules comes from the use of generics in VHDL. These generics are used for loop variables of VHDL GENERATE statements. In standard VHDL, the value associated with the generics is assigned by the higher level instantiating description, but in GNS the values are assigned according to what is identified in the circuit. Whenever a recognized structure is important for the user, the tool can be programmed to generate automatically, through ACTIONs, a behavioral description of the entire structure using the computed generic variables.
In the first phase, GNS transparently uses the FCL pattern-matching technology integrated in Yagle to identify transistor level blocks. In the second phase, GNS tries to apply the hierarchical rules from the lowest level of the hierarchy composed of the recognized transistor level blocks. The rules are applied in order of their hierarchical dependence up to the top level of the hierarchy. For each recognized instance, GNS executes an action if one has been provided by the user. The action is written in interpreted C code to which the identified values of the rule generics are passed as parameters. The nature of the action is evidently highly customizable, but an obvious application is the generation of a behavioral description customized to the identified structure.
In general, the GNS command is used as follows :
yagle -gns [options] input_name |
GNS reads the transistor net-list given by input_name. If input_name corresponds to the top level of a hierarchical net-list, then this net-list is first flattened. The hierarchical recognition is then performed until all the rules have been exhausted. The netlist is then partitioned into recognized and non-recognized parts. The standard Yagle automatic functional abstraction is performed on the non-recognized part, with all options of Yagle being taken into account. A VHDL or Verilog description for this is generated with the name <input_name>_yagcore, in a addition a structural Netlist is generated (in the format specified by avtOutputNetlistFormat) regrouping the recognized and non-recognized parts with the name <input_name>_yagroot. However, using the behavioral API (beg_API), it is possible to obtain a single file <input_name>.vhd.
GNS can also be executed as :
yagle -xg [options] input_name |
In this mode execution terminates after the recognition phase and the transistor netlist of the non-recognized parts of the circuit is generated (in the format specified by avtOutputNetlistFormat) instead of the behavioral description.
All the options available to Yagle are available to GNS to control the functional abstraction of the unrecognized parts.
<input netlist>_yagroot.<vhd|v|spi> | |
This file contains a structural description regrouping the blocks recognized by the GNS module and the remainder of the transistor netlist. | |
<input netlist>_yagcore.<vhd|v|spi> | |
Depending on the execution mode, this file contains either an automatically abstracted behavioral model of the unrecognized remainder of the transistor netlist, or the transistor netlist itself. | |
<input netlist>.<vhd|v> | |
If all the recognized blocks are given a behavior using the behavioral API (beg_API), this file will replace the two previous and will contain the merge of all the behaviors including the behavior automatically generated by YAGLE. |