This document explains:
- The tool capabilities and typical applications
- The internal structure of the tool
- How the tool integrates in custom design flows
- How to perform static timing analysis at transistor-level
- How to perform crosstalk analysis at transistor-level
- How to perform timing abstraction at transistor-level
- How to deal with big designs
Documentation issued and compliant with Avertec Release 3.4p5.
Please, contact support@avertec.com for any problems relating to this manual.
Avertec Copyright (c) 1998-2006 All Rights Reserved
|