Table of Contents
1. Input Files
2. Output Files
3. Log Files
4. Configuration Variables
5. Tcl Interface
6. Error Codes
Chapter 1 Subsections
1. Input Files
1. 1. Technology File and Netlist
1. 1. 1. SPICE
Expressions and Values
User-defined Functions
MOSFET
MOSFET Models
JFET
Junction Diode
Resistance
Capacitance
Subcircuit Instance
Independant Voltage Source
Supported Voltage Sources: Scenario 1
Supported Voltage Sources: Scenario 2
Supported Voltage Sources: Scenario 3
Supported Voltage Sources: Scenario 4
Supported Voltage Sources: Scenario 5
Supported Voltage Sources: Scenario 6
File Inclusion
Subcircuit
Parameters
Temperature
Scale Factor
Global Nodes
1. 1. 2. VERILOG
1. 1. 3. VHDL
1. 2. Parasitics
1. 2. 1. DSPF Used for Connectivity
1. 2. 2. DSPF Used for Back-Annotation
1. 2. 3. SPEF
1. 3. Timing Characterizations
1. 3. 1. Liberty
1. 3. 2. TLF
1. 4. INF Design Specific Configuration
1. 4. 1. Description
SDC input file
User-defined INF file
1. 4. 2. General
1. 4. 3. Disassembly Directives
IGNORE
CONSTRAINT
MUTEX
INPUTS
STOP
DIROUT
DLATCH
CKLATCH
PRECHARGE
NOTLATCH
MARKSIG
MARKTRANS
1. 4. 4. Timing Directives
BREAK
BYPASS
FALSEPATH
INTER
PINSLOPE
PATH DELAY MARGIN
NOFALLING - NORISING
CONNECTOR DIRECTIONS
RC - NORC
NOCHECK
DONOTCROSS
1. 4. 5. Timing Abstraction Directives
Parameterization of Lookup Tables
SLOPEIN
CAPAOUT
CLOCK CONNECTORS
1. 4. 6. STA Directives
General Header
CLOCK CONNECTORS
ASYNCHRONOUS CLOCK GROUPS
EQUIVALENT CLOCK GROUPS
MULTIPLE CLOCK PRIORITY
SPECIFY INPUT CONNECTORS
VERIFY OUTPUT CONNECTORS
Example of Stability Specification File
1. 4. 7. Crosstalk Directives
CROSSTALK MUTEX
1. 4. 8. Correspondencies INF / Tcl