The files and scripts needed for this example can be found in:
$AVT_TOOLS_DIR/tutorials/yagle/rom/ |
This example shows the application of Yagle in the case one wants to verify or to retrieve the content of a ROM. We have here three designs of a ROM of 256 words of 8 bits, programmed in three different ways:
The reference VHDL model of r256x8_1, r256x8_5 and r256x8_5 are respectively described in the files r256x8_1.vbe, r256x8_5.vbe and r256x8_6.vbe. Here is the reference VHDL model of r256x8_1:
ENTITY r256x8_1 IS PORT( adr : IN BIT_VECTOR(7 DOWNTO 0); ck : IN BIT_VECTOR(0 TO 1); f : OUT BIT_VECTOR(0 TO 7); vdd : IN BIT; vss : IN BIT ); END r256x8_1; ARCHITECTURE VBE OF r256x8_1 IS SIGNAL m_out : BIT_VECTOR (0 TO 7); BEGIN F = m_out WHEN (ck = B"00") ELSE B"00000000"; WITH adr(7 DOWNTO 0) SELECT m_out(0 TO 7) = B"00000000" WHEN B"00000000", B"00000001" WHEN B"00000001", B"00000010" WHEN B"00000010", B"00000011" WHEN B"00000011", B"00000100" WHEN B"00000100", B"00000101" WHEN B"00000101", B"00000110" WHEN B"00000110", B"00000111" WHEN B"00000111", B"00001000" WHEN B"00001000", B"00001001" WHEN B"00001001", B"00001010" WHEN B"00001010", B"00001011" WHEN B"00001011", ... B"11111110" WHEN B"11111110", B"11111111" WHEN B"11111111"; END VBE; |
To perform the abstraction of those designs, the line avt_config yagleTristateIsMemory yes has been added in the script.
The run.tcl commands generate the VHDL behavioral descriptions r256x8_1.vhd, r256x8_1.vhd and r256x8_6.vhd.
The content of the ROM can then be retrieved with a simple logic simulation.
The following screenshot displays the simulation trace r256x8_1.vcd of r256x8_1.vhd (data = address).