RE: [oc] DPLL

["Taiyi Cheng" <taiyich@palmmicro.com>]

Hi, You can consider to use ealy-late gate synchronization loop to recover
the bit clock for your Bluetooth uC.



-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
Behalf Of Jamil Khatib
Sent: Friday, November 16, 2001 1:23 PM
To: cores@opencores.org; liors@flextronicsdesign.co.il
Cc: bluetooth@opencores.org
Subject: Re: [oc] DPLL



Hi,
I need such block in my bluetooth controller which can performs bit
synchronization and clock recovery.
One suggestion was to perform oversampling, but this extracts the
incoming bits based on local clock only and does not recover the
original clock.
Is this approach enough or I should implement an equalizer? or one of
approaches mentioned by Lior?

Note: the bluetooth needs two levels of synchronization
- Bit level (which I described above)
- Packet level which can be recovered using Access code correlator as
described in the BT standard.
- Moreover the Master and slaves must be synchronized as in the BT
standard.

Regards,
Jamil Khatib

Lior Shtram wrote:

> Hi,
>
> This is much too simplistic. When the channel acts as a sort of a
> filter, you get ISI and you need an equalizer. This will not only
> effect
> the bit clock sync but also phase sync and performance of the
> reciever.
>
> This is however not a must in all systems, and does not relay on
> delay.
> Fading only makes your SNR worse which effects everything.
> There are many methods to recover bit clock, to name a few:
> 1. Pass the signal through a non-linear filter, and filter it around
> the
> bit clock frequency.
> 2. Phase lock loop with feedback being the (S(clock-delta) -
> S(clock+delta))*(sign(S(clock))
>     * not completely sure I got it right here, but this is about
> right
> anyway
>
> you can get a lot of information about bit clock recovery from text
> books in digital communication.
>
> So equalizer or no equalizer depends on your channel and is not a
> must
> for many satellite communication systems (doesn't hurt though usualy).
>
> hope that helps, please send any questions.
>
> regards,
> Lior
>
> haoguang.guo@philips.com wrote:
>
> >Hi,
> >           I have a problem about  bit synchronization when use QPSK
> in satellite communication. When design the demodulator , how can i
> get the
> >bit clock?  Some one said because of the fading and unknown delay ,
> you can not synchroniza to the transmitter . so must  use the
> equalizer to estimate the channel. Is it right?
> >
> >
> >
> >
> >
> >
> >
> >
> >"Sam Gladstone" <samg@t-and-t.com>@opencores.org on 11/15/2001
> 06:29:28 AM
> >
> >Please respond to cores@opencores.org
> >
> >Sent by:  owner-cores@opencores.org
> >
> >
> >To:     <cores@opencores.org>
> >cc:      (bcc: Haoguang Guo/SHA/SC/PHILIPS)
> >Subject:  Re: [oc] DPLL
> >Classification:
> >
> >
> >
> >I take it you are demodulating back to a certain softbit size?
> >There is several books out there that are pretty good. I will find
> the
> >one I used when we were writing an 802.11a phy for a company.
> >
> >The main idea is to demodulate each dimension of the
> QPSKconstellation data
> >seperately by
> >breaking the real and imaginary up into two seperate demodulations.
> Linear
> >extrapolations can be used to generate softbits for a first order
> method.
> >There are more cost effective, but
> >harder to understand methods available as well.
> >(Assuming that you have already done the proper power and phase
> >corrections.)
> >I think the number of softbits generated looks like this table.
> >BPSK - 1 softbit per constellation
> >QPSK - 2 softbits per constellation
> >QAM-16 - 4 softbits per constellation
> >QAM-64 - 6 softbits per constellation
> >(QAMs get nasty because they are like combinations of different
> codings that
> >have
> >to have multiple softbits generated per demension because of grey
> coding
> >with the
> >modulution module. Yuck! )
> >
> >I will try to find the book name and send it out.
> >
> >Regards,
> >  Sam
> >
> >----- Original Message -----
> >From: <aolmo@grupoeyp.com>
> >To: <cores@opencores.org>
> >Sent: Wednesday, November 14, 2001 9:24 AM
> >Subject: [oc] DPLL
> >
> >
> >>Hi,
> >>
> >>I take the liberty disturbing you.
> >>I am a friend from Taiwan.
> >>After reading your posts on Web, I know you are a professional
> >>communication designer.
> >>Now I am designing QPSK demodulator for wireless Lan with verilog.
> >>Where can I find more helpful material, such as verilog code for
> DPLL.
> >>Please kindly to give me some advice.
> >>Thank you a lot!
> >>--
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> >
> >>
> >
> >
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> >
> >
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>
>
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--
   Jamil Khatib
OpenCores Organization
http://www.opencores.org




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