Re: [oc] HLLs vs HDLs

[Billditt@aol.com]

I use SystemC and both Verilog and VHDL.
SystemC is used to model algorithms, system
interaction. The HDL's are used to build
an RTL based design which can be synthesized.
We often use all 3 to model, test and build
a system.

All 3 languages can be used to do Design Verification.
VHDL is the better of the HDL's for this, with Verilog
improving by adding more abstract functionality (such
as user defined types, unconstrained arrays, etc.).
SystemC has all that and more, but the others often
prove adequate enough by themselves.
 
You can synthesize SystemC, but you must constrain your
code so it ends up like RTL. And not a lot of designers
know SystemC.

SystemC has the advantages of C++, which it is built upon.
Additionally, it adds classes so that one can do concurrency,
event synchronization, hw types like bit, bit vectors, channel communications.

The HDL's are improving, adding more modeling, verification functionality. The synthesis tools are improving, so you can synthesize what used to be considered behavioural. 

I really dont see SystemC replacing the HDL's. I do see it
augmenting them, used as means of modeling architectures, etc. The HDL's are evolving, and industry wide have a large
user base. I dont see them going away any time soon.
was previously
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