Re: [oc] pseudo random generator verilog code source

[Marko Mlinar <markom@opencores.org>]

Here:

reg [31:0] poly;

always @(posedge clk or posedge reset_poly)
  if (reset_poly) poly <= #1 32'hdeaddead;
  else poly <= #1 {poly[30:0], poly[17] ^ poly[4]};

On Thursday 19 September 2002 09:54, Dharmeshbhai PATEL wrote:
> Hi list,
>
> Does any one has an idea where i can get the verilog code source
> for a pseudo random generator (number or signal) ?
>
> Please let me know.
>
> Thanks in advance.
> D.PATEL
>
>
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