[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [oc] urgent
Aloha!
AmitShah124@hotmail.com wrote:
> in our first semester we are supposed to do a project on vlsi. the
> suggested topics are as follows:
>
> Network Interface Circuit and Cache Coherency for
> multiprocessors
> DES Data Encryption.
>
> Digital Filter with programmable coefficients.
>
> Memory structures such as RAM/ROM.
>
> BCD Arithmetic Logic Unit.
>
> Simple CPU.
>
> Universal Synchronous/Asynchronous Receiver/Transmitter (USART).
>
> Ethernet Interface (send data on serial link, retransmit on collision,
> snoop at bus).
>
> Floating-point multiplier (multiply two numbers in some format).
>
> Alarm clock (set time, set alarm, on/off, snooze).
>
> Now i want some help from you regarding this project... can you tell me
> which project should i go for and you can suggest something if you
> have in mind...
>
> I just want general guidance and am ready to work hard..
> I AM THINKING ABOUT DOING NETWORK INTERFACE OR DEC..
> I HAVE TO GIVE THE BLOCK DIAGRAM AND SPECIFICATIONS SO IF YOU
> COULD PLEASE HELP ME..
I would recommend selecting something that is (a) non-trivial and (b) have
good, clearly defined results. Also, try to figure out which assignment makes
most sense for you as a way to become the type of engineer you are aspiring to be.
If you for example are planning to work with interfaces, I/Os etc, then target
that. If it's processor design and u-architecture, then target some
interesting part of a CPU. The cache coherency thing is a good, non trivial
problem in that respect.
The digital filter (unless we are talking about several tens of taps, low
HE-resources and interesriting architectures) and alarm clock sounds way to
simple for being a good challange. The CPU is open ended (it requires so much
side issues and it's hard to know if you are "right"), Ethernet IF is a _big_
task, esp if you want to be compatible with the rest of the world. A simple
Ethernet MAC is an ok assignment though.
The DES standard is old and there are better/more interesting/challenging
ciphers to target. The good thing though is that there are good test cases
that you can use to verify functionality.
What is the target result? RTL-design/architecture on paper?
Verilog/VHDL-implementation? Design running in a FPGA?
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
----------------------------------------------------------------------
InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden
Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02
E-mail: joachim.strombergson@informasic.com Home: www.informasic.com
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml