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[cvs-checkins] can/rtl/verilog can_bsp.v can_btl.v can_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] can/rtl/verilog can_bsp.v can_btl.v can_top.v
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Wed, 11 Jun 2003 13:21:53 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/06/11 13:21:52

Modified files:
	rtl/verilog    : can_bsp.v can_btl.v can_top.v 

Log message:
	When switching to tx, sync stage is overjumped.

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