[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] uart16550/rtl/verilog uart_defines.v uart_regs ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/rtl/verilog uart_defines.v uart_regs ...
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Wed, 11 Jun 2003 15:38:07 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	03/06/11 15:38:06

Modified files:
	rtl/verilog    : uart_defines.v uart_regs.v uart_rfifo.v 

Log message:
	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] can/rtl/verilog can_bsp.v can_btl.v can_top.v
Next by Date: [cvs-checkins] pci/bench/verilog pci_testbench_defines.v pci_ ...
Prev by thread: [cvs-checkins] pci/bench/verilog pci_testbench_defines.v pci_ ...
Next by thread: [cvs-checkins] can/rtl/verilog can_bsp.v can_btl.v can_top.v
Index(es):
- Date
- Thread