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Re: [openrisc] Another issue...
> It occurs to me that the real problem is the
> architectural simulator is executing in series,
> whereas the real RTL code will execute both units
> in parallel.
Arch simulator is not implementation simulator. Arch simulator should model
only OR1K architecture and has nothing to do with OR1200.
>
> So, in order to fix this problem, I have rewritten
> the address calculation schemes wherever I can find
Great.
> This seems to fix this issue, and does not affect
Great.
regards,
Damjan