Re: [openrisc] Address pipeline during exception...

["Damjan Lampret" <lampret@opencores.org>]

> by simply setting pc_phy to pc.

OK.

>
> This raises the more interesting question though of
> what does happen during an exception. The Or1k
> manual does not state how many cycles it takes for
> an exception to be processed. I'm guessing 2
> because it must reload the instruction pipeline. Is this
> correct?

It depends on implementation. It isn't defined by the architecture itself.

>
> The simulator needs to be modified to account for
> this, because other peripherals, such as the serial
> port, are still executing and the timing between them
> needs to be correct.

Well in real system doesn't matter if CPU takes more or less cycles to do an
exception since serial port is completely independent. So I don't understand
what is the relation between serial port and CPU's exceptions?

>
> I've added a cycle_delay register that is set whenever
> an exception occurs and is processed by toplevel.c to
> ignore the cpu unit but update all the peripherals to
> accomodate this condition.

OK.

Chris, feel free to modify whatever in or1ksim that doesn't follow current
architectural specification. You can also add features that are not
specified by the architecture.

regards,
Damjan