Re: RE: [openrisc] Operating frequency after synthesis with ASIC lib.

[Damjan Lampret <lampret@opencores.org>]

On 28 Mar 2002 05:57 CET you wrote:

> Thank you so much, Damjan
> 
> May I ask you when the updates will be in the CVS?

It will happen gradually, during this and next week. Additional update will happen in second half of the April. I don't know how much optimizations will come into CVS during next 10 days, since one requirement is that they are also tested on FPGA prototype board (running uClinux) beside the normal verification regression simulations.

> 
> Let me intoduce my work, briefly.
> Currently, I am designing an SOC targeted to network security applications,
> and I am looking for a microprocessor which can be equpped in the SOC - OR1200 is a good candidate.

BTW you can also disable some of the units you might not need. For example if your application does not require MMU, you can disable it.

> OR1200 is neat and has well structured software development tool chain.

Thanks, we are all trying our best to create a high quality processor family.

> So, now I am evaluating OR1200 with samsung 0.25um ASIC library - I will also evaluate OR1200 with TSMC 0.25um/Artisan lib.
> 
> -----The first result of timing evaluation with samsung lib. shows "11.8ns" delay for the most critical path.
> -----The path starts at data output of ICACHE and ends at the or1200_ic_top/saved_addr_r_reg[5]. 
> 
> The performance(op. freq.) requirement for the microprocessor is more than 130 MHz.
> I want to finish the performance evaluation in a week to proceed to the next phase of project.
> If there are anything I can help you to build the next version of OR1200 distribution, Pls let me know.

If you can send the critical timing paths, that would be nice. I don't run .25u anymore, only .18u and these are different.
Also please do not send any proprietary information to the list.

regards,
Damjan

--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml