RE: [openrisc] Operating frequency after synthesis with ASIC lib.

["jinhyuk" <jinhyuk@nexilion.com>]

Thank you so much, Damjan

May I ask you when the updates will be in the CVS?

Let me intoduce my work, briefly.
Currently, I am designing an SOC targeted to network security applications,
and I am looking for a microprocessor which can be equpped in the SOC - OR1200 is a good candidate.
OR1200 is neat and has well structured software development tool chain.
So, now I am evaluating OR1200 with samsung 0.25um ASIC library - I will also evaluate OR1200 with TSMC 0.25um/Artisan lib.

-----The first result of timing evaluation with samsung lib. shows "11.8ns" delay for the most critical path.
-----The path starts at data output of ICACHE and ends at the or1200_ic_top/saved_addr_r_reg[5]. 

The performance(op. freq.) requirement for the microprocessor is more than 130 MHz.
I want to finish the performance evaluation in a week to proceed to the next phase of project.
If there are anything I can help you to build the next version of OR1200 distribution, Pls let me know.

regards,
Jinhyuk

> 
> Hi jinhyuk,
> 
> it is all what you said. First results with the Virtual Silicon 
> libraries were always worse than with Artisan (especially 
> memories). Second false paths are not listed yet, and they are there.
> 
> Additionally since last optimizations, the OR1200 went through 
> some functional changes. During that periods the timing is not so 
> important as is functional correctness of the core. Now it is 
> going through final timing optimization. There are already some 
> important timing optimizations, however they are not yet in the CVS.
> Also DC and simulation scripts will soon be updated in the CVS as well.
> 
> regards,
> Damjan
> 
> On 27 Mar 2002 04:54 CET you wrote:
> 
> > Hi, my name is jinhyuk
> > 
> > I have downloaded the or1200 implementation - It looks cool!!.
> > Thanks the works.
> > 
> > My question is about achievable operating freq. of or1200 for 
> ASIC implementation.
> > The document says it operates at 250Mhz for 0.18um UMC/Virtual 
> silicon lib., worst-case, post-layout.
> > 
> > I sythesized or1200 with samsung 0.25um.
> > I expected that the synthesized or1200 can operate at least 
> 150Mhz worst-case, pre-layout.
> > But, according to STA report, the maximum frequecy is about 
> 100Mhz - big gap!!
> > I can't understand what makes the biggg difference.
> > 
> > It may be caused by library performance (speed).
> > How about the performance of virtual silicon library?
> > Is it better than other standard cell libraries? For example, 
> Artisan library.
> > Samsung lib. has almost same performance as Artisan library.
> > 
> > Are there any false paths or multi-cycle paths in or1200 design?
> > There's no disable timing commands in synthesis scripts 
> included in or1200 distribution.
> > 
> > Any suggestions or comments will be very halpful for me.
> > Thank you in advance.
> > 
> > /Jinhyuk Yang
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