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Allright, here are "the goods!"
Unfortunately, there is no testbench for this core. It was developed through many design iterations in an actual Xilinx XC2V200 SpartanII FPGA, with the aid of a HP16500 series logic analyzer. This proved to be much faster than simulating, (or at least that is how we felt) since the serial-ports need thousands and thousands of clock cycles between output transitions... Or maybe we were just too "lazy" to make a testbench! But, this core does work. It is just over 1000 lines of Verilog code, with lots of comments, and it took many hours to debug it.
Downloads:
rs232_syscon_1_01_xsoc.zip. This file contains the updated rs232_syscon, which supports muxing of the stb_o and we_o lines (in addition to the adr_o lines, which were already muxed between rs232_syscon and the normal bus master.) This file shows how the rs232_syscon can be connected to a host microcontroller. In this case the microcontroller is a 16-bit RISC design, modified from the original XSOC project. This entire design takes up only about 900 Xilinx Virtex slices. The rs232_syscon uses more than half of this logic.... The RISC microcontroller runs at about 32 MHz on the XC2S200 SpartanII chip, without any floorplanning and without any aggressive timing constraints.
rs232_syscon_soc1.zip. This file contains the rs232_syscon connected to a set of 8 registers, 1 of which is read only (uses "reg_8_pack.v" for the registers). It is a good example of how the tri-state data bus connects to the registers. It also has an lcd-panel test block connected to the outputs of the registers, but you can easily delete that part.