Re: [oc] SoC bus review

[Damjan Lampret <lampret@opencores.org>]

> So far, all I've decided is that each FPGA module should include two sets of
> JTAG
> signals.  One for configuration, one for testing and emulation.  Any more

Just triggered a thought in my mind. (not related to inter FPGA communication
and maybe not even to SoC buses)

How about scan chain for ASIC verification. Could this be (optional) part of SoC
bus? IP cores beside "normal" bus interface also have scan chain interface.
Should we define this scan chain interface?

regards,
Damjan