[oc] synthesize and pipeline programming

[jae lim <jlim0011@yahoo.com>]

Hello Everyone

My name is Jay and I am recently working on some RISC
processor verilog Coding. I have some questions, if
your guys could help me out, I will be more than thank
you...

1) For the pipelined Simple RISC processor, is it
easier for the synthesis tool to optimize the code if
I implemented as five stage pipeline as small modules
as possible or it doesn't matter even if I implement
it as a whole big module? If the former is the case,
should I divide the module as five stages, including
every functional units into the stage modules or
should I put the functional units as individual
modules?

2) If I am trying to do the formal verification,
assume that I have already have the synthesized
netlist based on certain vendor 's library using the
synthesize tool, Design Compiler, how can I feed the
netlist into the HDL simulator, get the simulation
result and then compare with the non-synthesized
simulation results? I guess my question is : Can the
HDL simulator recognize the library cells?

Any suggestions will be greatly helpful!!

Have a nice weekend.

Jay


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