Re: [oc] Programs in Xilinx Block RAM

[peddiyogeshwar@vsnl.net]

Hi,

Use Core generator to generate your particular core.

The inputs to the Core generator
1. Your options for the Block RAM inputs and outputs, that is whether it should be a Single Port, Dual Port etc which you have to choose from the Core generator GUI.
2. A coefficient file called "*.coe"file, the format of which you can get from the user manual for the Block RAM.

>From these two inputs, you will get your desired *.edn file (core with your desired boot program loaded into it).

Also the core generator generates a file called *.ver file. This file contains the templates of the Core that you need to instantiate into your verilog code. The Core generator system generates the template file for vhdl also, but I am not sure about the extension name for the file.

For Synthesis purpose, you do not need the EDIF netlist of the block ram core with the boot program in it. You just have to insert the templates, and run. But make sure that the the `include directives point to the exact location of your XilinxCoreLib directory.

For the Place and Route you will definitely require the *.edn core files. They should be placed in your project directory.

Hope this helps.
All The Best 
Yogeshwar



shehryar.shaheen@ul.ie wrote
Hi,
     I intend to incorporate the Mini-Risc Core by Rudolf Usselmann with an FTDMA (similar to ByteFlight) controller.

What I need to know is how to synthesize programs in the program memory (Xilinx Block RAM). The hex2v program generates
a .rom file which is used within the test bench for simulations but for sysnthesis how to synthesize the program within the Block RAM
or if there is a way to dynamically download programs in the Block RAM.

I am using Xilinx WebPack and XC2S200 -5C Spartan-II  FPGA.

In the $WebPackRoot/bin/nt directory there is a generatecore.exe utility. I rough guess I have that I would have to generate
the Block RAM core with the program in it and then intantiate it in the Desisgn before synthesis. The generate core utility gives the following message

C:\xilinx_webpack\bin\nt>generatecore
Usage: generatecore [-cell <cellName>] [-component <componentName>] [-targetArch

<targetDeviceFamily>] [-library <libraryName>] [-package <packageName>]
[-outputFile <outputFileName>] [-outputDirectory <outputDirectory>] [-p
{<ppair>}] [-a {<apair>}] <simName>


But guessing and experimenting won't work (at least not fast enough). I'll be grateful if Rudolf Usselmann or any one else can 
answer.

Thanks in anticipation and kind regards

Shehryar 


    
 





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