Re: [oc] design methodology

[Richard Herveille <richard@asics.ws>]

Depends on what you put in a function.

I like to use function (both in VHDL and Verilog) for up/down counters, 
absolute value etc.

As long as the contents are simple, and you put registers in your main-code 
than there's no difference.

At the end I guess it all comes down to coding styles and common sense.
Know what you type, know what you ask the compiler to do.


> hi all,
>
> Some designs are writen using procedures and functions instead using
> separate entities and architectures. I would like to know if it has effect
> on time, area, consume...does anybody know de difference?
>
> thanks in advance to all of you, leire


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml