Mail Index

• Thread Index

• Re: [oc] core for FFT/IFFT (1024 point)for 802.11a protocol
  • From: z82302@msn.com
• Re: [oc] Ethernet crc32 VHDL anyone?
  • From: "kinysh asdf" <kinysh@hotmail.com>
• Re: [oc] Ethernet crc32 VHDL anyone?
  • From: "Amani" <q_f82@sina.com>
• Re: Re: [oc] ARM Core
  • From: "ritesh" <ro_sharma@rediffmail.com>
• Re: Re: [oc] ARM Core
  • From: "ritesh" <ro_sharma@rediffmail.com>
• RE: [oc] Ethernet crc32 VHDL anyone?
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• Re: [oc] Ethernet crc32 VHDL anyone?
  • From: Colin Marquardt <c.marquardt@alcatel.de>
• [oc] Ethernet crc32 VHDL anyone?
  • From: deepak_1980_r@hotmail.com
• Re: [oc] test_bench
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] test_bench
  • From: Colin Marquardt <c.marquardt@alcatel.de>
• [oc] test_bench
  • From: leire.rubio@alumni.eps.mondragon.edu
• Re: [oc] ARM Core
  • From: nissimd@aeronautics-sys.com
• Re: [oc] Async reset: active high or active low?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Async reset: active high or active low?
  • From: Niclas Hedhman <niclas@hedhman.org>
• Re: [oc] Async reset: active high or active low?
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] Async reset: active high or active low?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Async reset: active high or active low?
  • From: <cyrano@nerim.net>
• Re: [oc] Async reset: active high or active low?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Async reset: active high or active low?
  • From: Niclas Hedhman <niclas@hedhman.org>
• Re: [oc] Async reset: active high or active low?
  • From: <cyrano@nerim.net>
• Re: [oc] 8255 PPI source code
  • From: "MikeJ" <mikej@freeuk.com>
• Re: [oc] Async reset: active high or active low?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Async reset: active high or active low?
  • From: "Haytham Azmi" <haythamazmi@hotmail.com>
• Re: [oc] Async reset: active high or active low?
  • From: <cyrano@nerim.net>
• [oc] Async reset: active high or active low?
  • From: Allan Herriman <allan_herriman@agilent.com>
• RE: [oc] UART16550 core and 10/100 Base-T Core
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• RE: [oc] UART16550 core and 10/100 Base-T Core and GPIO Core
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• RE: [oc] UART16550 core and 10/100 Base-T Core
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• RE: [oc] UART16550 core
  • From: "Igor Mohor\(opencores\)" <igorm@opencores.org>
• RE: [oc] UART16550 core
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• Re: [oc] Adder issues ?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Adder issues ?
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] Adder issues ?
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] Adder issues ?
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] Adder issues ?
  • From: NansonHuang@ITRI.ORG.TW
• Re: [oc] UART16550 core
  • From: khchang@haco.co.kr
• Re: [oc] Trade off between area and power ?
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] Trade off between area and power ?
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] Trade off between area and power ?
  • From: NansonHuang@ITRI.ORG.TW
• Re: [oc] 8255 PPI source code
  • From: veena_3_2003@yahoo.co.in
• RE: [oc] VHDL Process statement
  • From: "Radwin Zagala" <rzagala@softhome.net>
• [oc] =?gb2312?B?tPC4tDogW29jXSBWSERMIFByb2Nlc3Mgc3RhdGVtZW50?=
  • From: lin.sheng@zte.com.cn
• [oc] VHDL Process statement
  • From: twebel@gmx.de
• RE: [oc] video_compression_systems document
  • From: "Naveena Padmaraju" <naveena.padmaraju@wipro.com>
• Re: [oc] video_compression_systems document
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] Suggesting H263 codec core
  • From: ha_delbari@yahoo.com
• Re: [oc] Hi, may we be friends?
  • From: "Chenbo Liu" <philewar@icc.sh.cn>
• RE: [oc] PS/2 mouse & keyboard Wishbone core
  • From: Rudolf Usselmann <rudi@asics.ws>
• RE: [oc] PS/2 mouse & keyboard Wishbone core
  • From: "Igor Mohor\(opencores\)" <igorm@opencores.org>
• [oc] Hi, may we be friends?
  • From: "liu yuxue" <yuxue_liu@msn.com>
• Re: [oc] PS/2 mouse & keyboard Wishbone core
  • From: Marko Mlinar <markom@opencores.org>
• [oc] video_compression_systems document
  • From: "kinysh asdf" <kinysh@hotmail.com>
• RE: [oc] NEWS-FLASH: Free VHDL to Verilog Translator
  • From: "liu, zhigang" <liu_zhigang@emc.com>
• Re: [oc] NEWS-FLASH: Free VHDL to Verilog Translator
  • From: yanzhang1999@hotmail.com
• [oc] PS/2 mouse & keyboard Wishbone core
  • From: "Daniel Quintero" <danielqg@infonegocio.com>
• FW: [oc] UART16550
  • From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>
• RE: [oc] How to model capacitor in Verilog??
  • From: "sphuynh" <sphuynh@micron.com>
• RE: [oc] How to model capacitor in Verilog??
  • From: "kinysh asdf" <kinysh@hotmail.com>
• RE: [oc] How to model capacitor in Verilog??
  • From: sphuynh <sphuynh@micron.com>
• Re: [oc] UART16550
  • From: "Steve Tate" <tate@aos-inc.com>
• [oc] How to model capacitor in Verilog??
  • From: kokloon@hotmail.com
• RE: [oc] UART16550
  • From: "Harvey, Wilbur" <Wilbur.Harvey@spirentcom.com>
• [oc] Xilinx -> ALdec Core compatibility
  • From: kartik@opencores.org
• Re: [oc] async/sync reset.
  • From: manxi wang <wangmanxi@yahoo.com>
• Re: [oc] verilog to vhdl converter
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] UART16550
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] Re: code for usart
  • From: roopa_ranganath@hotmail.com
• Re: [oc] WTB & MVB protocols
  • From: Armando Astarloa <jtpascua@bi.ehu.es>
• [oc] UART16550
  • From: tate@aos-inc.com
• Re: [oc] WTB & MVB protocols
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• [oc] WTB & MVB protocols
  • From: "vdesign" <vdesign@satyam.net.in>
• Re: [oc] verilog to vhdl converter
  • From: leire.rubio@alumni.eps.mondragon.edu
• Re: [oc] DCT Project [ROM64 and others]
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] async/sync reset.
  • From: "kinysh asdf" <kinysh@hotmail.com>
• [oc] Inquiry
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] IEEE802.11 MAC core
  • From: youlong@eyou.com
• [oc] DCT Project [ROM64 and others]
  • From: Héctor Orón Martínez <hecormar@teleco.upv.es>
• [oc] Can I get the time integrating correlator's verilog source code?
  • From: uzunlarovunc@hotmail.com
• Re: [oc] How Do I Make UART EDIFs in Macros for Use in Projects?
  • From: Armando Astarloa <jtpascua@bi.ehu.es>
• Re: [oc] How Do I Make UART EDIFs in Macros for Use in Projects?
  • From: "Michael Ayton" <mike_ayton@dsl-only.com>
• Re: [oc] async/sync reset.
  • From: John Sheahan <jrsheahan@optushome.com.au>
• [oc] How Do I Make UART EDIFs in Macros for Use in Projects?
  • From: "Benson Wong" <bjwong@pacbell.net>
• Re: [oc] async/sync reset.
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Open Core Forth Processor
  • From: dyy1511@sina.com
• Re: [oc] async/sync reset.
  • From: <cyrano@nerim.net>
• Re: [oc] ARM Core
  • From: "ritesh" <ro_sharma@rediffmail.com>
• Re: [oc] projects
  • From: Shehryar Shaheen <shehryar.shaheen@ul.ie>
• Re: [oc] async/sync reset.
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] async/sync reset.
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] async/sync reset.
  • From: <cyrano@nerim.net>
• Re: [oc] async/sync reset.
  • From: <cyrano@nerim.net>
• Re: [oc] Xscale, etc. and IP
  • From: Holger Baxmann <hbaxmann@mac.com>
• Re: [oc] Xscale, etc. and IP
  • From: Jayaprakash Balachandran <edpc108@yahoo.com>
• Re: [oc] projects
  • From: Holger Baxmann <hbaxmann@mac.com>
• Re: [oc] Xscale, etc. and IP
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• [oc] projects
  • From: "albert raj a" <allbut@lycos.com>
• Re: [oc] async/sync reset.
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] ARM Core
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] ARM Core
  • From: porschen@ieee.org
• [oc] async/sync reset.
  • From: nico <nico@seul.org>
• Re: Re: [oc] PLL vs DLL
  • From: "kinysh asdf" <kinysh@hotmail.com>
• Re: [oc] Xscale, etc. and IP
  • From: "kinysh asdf" <kinysh@hotmail.com>
• [oc] Re: Fwd: [Fwd: Fwd: Fw: I love India]
  • From: "ritesh" <ro_sharma@rediffmail.com>
• Re: [oc] [Fwd: Industry Gadfly "VHDL, the new Latin"]
  • From: Holger Baxmann <hbaxmann@mac.com>
• Re: [oc] Xscale, etc. and IP
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• [oc] [Fwd: Industry Gadfly "VHDL, the new Latin"]
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] or1200's or1200_ctrl.v
  • From: Marko Mlinar <markom@opencores.org>
• [oc] or1200's or1200_ctrl.v
  • From: "qcpassed" <qcpassed@sina.com>
• [oc] Xscale, etc. and IP
  • From: shr@chat.net
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: nico <nico@seul.org>
• [oc] need help about or1200's freeze logic
  • From: "qcpassed" <qcpassed@sina.com>
• Re: [oc] verilog to vhdl converter
  • From: John Sheahan <jrsheahan@optushome.com.au>
• [oc] z80 code
  • From: "Ian MacPherson" <ian@lavalink.com>
• Re: [oc] verilog to vhdl converter
  • From: Graham Seaman <graham@seul.org>
• Re: [oc] verilog to vhdl converter
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] verilog to vhdl converter
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [oc] verilog to vhdl converter
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] verilog to vhdl converter
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] verilog to vhdl converter
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Graham Seaman <graham@seul.org>
• Re: [oc] verilog to vhdl converter
  • From: John Dalton <john.dalton@bigfoot.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: John Dalton <john.dalton@bigfoot.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Niclas Hedhman <niclas@hedhman.org>
• Re: [oc] verilog to vhdl converter
  • From: Niclas Hedhman <niclas@hedhman.org>
• Re: [oc] VHDL Simulation Model for 24C02
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] VHDL Simulation Model for 24C02
  • From: ysli@ee.columbia.edu
• Re: [oc] help about or1k's dmmu
  • From: "qcpassed" <qcpassed@sina.com>
• [oc] help about or1k's dmmu
  • From: "qcpassed" <qcpassed@sina.com>
• Re: [oc] Final Year University Projects
  • From: Alexander Groisman <w3doctor@yahoo.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: nico <nico@seul.org>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Cyrano <cyrano@nerim.net>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Kevin Kilzer <kkilzer@adtron.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] verilog to vhdl converter
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] verilog to vhdl converter
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] UART16550 core
  • From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Johan Klockars <johan@klockars.net>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] Twofish implementation question
  • From: "henry_xb" <xxiaobin@263.net>
• [oc] Twofish implementation question
  • From: spyros_s@freemail.gr (spyros)
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: <cyrano@nerim.net>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Johan Klockars <johan@klockars.net>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] RE: [pci] PCI core ( LICENSING )
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] RE: [pci] PCI core ( LICENSING )
  • From: "Tadej Markovic" <tadejm@flextronics.si>
• [oc] Serila DAA in verilog
  • From: Tanveer Shariff <shariff_ics@yahoo.com>
• [oc] Synthzable rom
  • From: Tanveer Shariff <shariff_ics@yahoo.com>
• [oc] task usage in verilog
  • From: lin.sheng@zte.com.cn
• Re: [oc] design methodology
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] design methodology
  • From: Richard Herveille <richard@asics.ws>
• [oc] design methodology
  • From: leire.rubio@alumni.eps.mondragon.edu