RE: [oc] How to model capacitor in Verilog??

[sphuynh <sphuynh@micron.com>]

I haven't use it yet but I believe that is correct usage.

// Strength is large, medium, small
// Decay with trise = 0, tfall = 1, tdecay = 9
// trireg (strength) #(trise, tfall, tdecay) capacitor


-----Original Message-----
From: kokloon@hotmail.com [mailto:kokloon@hotmail.com] 
Sent: Wednesday, April 16, 2003 4:54 AM
To: cores@opencores.org
Subject: [oc] How to model capacitor in Verilog??


Hi all,

I am trying to model a capacitor using standard Verilog, but 
I have no idea how to do it...

Does anybody have any idea on this??
Issit like this??

trireg (large) #(0,1,9) capacitor

Thanks,
Kok Loon
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