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RE: [oc] Ethernet crc32 VHDL anyone?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- synopsys translate_off
LIBRARY lpm;
USE lpm.lpm_components.all;
-- LIBRARY SYNPLIFY;
-- USE SYNPLIFY.ATTRIBUTES.ALL;
LIBRARY work_ioc;
USE work_ioc.mem_init_file_pack_v4_0.ALL;
USE work_ioc.ul_utils.ALL;
USE work_ioc.blkmemdp_pkg_v4_0.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work_ioc.log.all;
ENTITY eth_crc IS
GENERIC(
Tp : time := 1 ns
);
PORT(
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Enable : IN STD_LOGIC;
Initialize : IN STD_LOGIC;
Crc : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
CrcError : OUT STD_LOGIC
);
END eth_crc ;
ARCHITECTURE flow OF eth_crc IS
SIGNAL CrcNext : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL r_Crc : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
---------------------------------------------------------------------------
process0 : PROCESS (Clk, Reset)
---------------------------------------------------------------------------
BEGIN
IF Reset='1' THEN
r_Crc <= x"ffffffff" after Tp;
ELSIF (Clk'EVENT) AND (Clk = '1') THEN
IF Initialize='1' THEN
r_Crc <= x"ffffffff" after Tp;
ELSE
r_Crc <= CrcNext after Tp;
END IF;
END IF; -- ELSIF (Clk'EVENT) AND (Clk = '1') THEN
END PROCESS process0;
CrcNext(0) <= Enable AND (Data(0) XOR r_Crc(28));
CrcNext(1) <= Enable AND (Data(1) XOR Data(0) XOR r_Crc(28) XOR r_Crc(29));
CrcNext(2) <= Enable AND (Data(2) XOR Data(1) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(29) XOR r_Crc(30));
CrcNext(3) <= Enable AND (Data(3) XOR Data(2) XOR Data(1) XOR
r_Crc(29) XOR r_Crc(30) XOR r_Crc(31));
CrcNext(4) <= (Enable AND (Data(3) XOR Data(2) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(30) XOR r_Crc(31))) XOR
r_Crc(0);
CrcNext(5) <= (Enable AND (Data(3) XOR Data(1) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(29) XOR r_Crc(31))) XOR
r_Crc(1);
CrcNext(6) <= (Enable AND (Data(2) XOR Data(1) XOR r_Crc(29) XOR
r_Crc(30))) XOR r_Crc( 2);
CrcNext(7) <= (Enable AND (Data(3) XOR Data(2) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(30) XOR r_Crc(31))) XOR
r_Crc(3);
CrcNext(8) <= (Enable AND (Data(3) XOR Data(1) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(29) XOR r_Crc(31))) XOR
r_Crc(4);
CrcNext(9) <= (Enable AND (Data(2) XOR Data(1) XOR r_Crc(29) XOR
r_Crc(30))) XOR r_Crc(5);
CrcNext(10) <= (Enable AND (Data(3) XOR Data(2) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(30) XOR r_Crc(31))) XOR
r_Crc(6);
CrcNext(11) <= (Enable AND (Data(3) XOR Data(1) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(29) XOR r_Crc(31))) XOR
r_Crc(7);
CrcNext(12) <= (Enable AND (Data(2) XOR Data(1) XOR Data(0) XOR
r_Crc(28) XOR r_Crc(29) XOR r_Crc(30))) XOR
r_Crc(8);
CrcNext(13) <= (Enable AND (Data(3) XOR Data(2) XOR Data(1) XOR
r_Crc(29) XOR r_Crc(30) XOR r_Crc(31))) XOR
r_Crc(9);
CrcNext(14) <= (Enable AND (Data(3) XOR Data(2) XOR
r_Crc(30) XOR r_Crc(31))) XOR r_Crc(10);
CrcNext(15) <= (Enable AND (Data(3) XOR r_Crc(31))) XOR r_Crc(11);
CrcNext(16) <= (Enable AND (Data(0) XOR r_Crc(28))) XOR r_Crc(12);
CrcNext(17) <= (Enable AND (Data(1) XOR r_Crc(29))) XOR r_Crc(13);
CrcNext(18) <= (Enable AND (Data(2) XOR r_Crc(30))) XOR r_Crc(14);
CrcNext(19) <= (Enable AND (Data(3) XOR r_Crc(31))) XOR r_Crc(15);
CrcNext(20) <= r_Crc(16);
CrcNext(21) <= r_Crc(17);
CrcNext(22) <= (Enable AND (Data(0) XOR r_Crc(28))) XOR r_Crc(18);
CrcNext(23) <= (Enable AND (Data(1) XOR Data(0) XOR
r_Crc(29) XOR r_Crc(28))) XOR r_Crc(19);
CrcNext(24) <= (Enable AND (Data(2) XOR Data(1) XOR
r_Crc(30) XOR r_Crc(29))) XOR r_Crc(20);
CrcNext(25) <= (Enable AND (Data(3) XOR Data(2) XOR
r_Crc(31) XOR r_Crc(30))) XOR r_Crc(21);
CrcNext(26) <= (Enable AND (Data(3) XOR Data(0) XOR
r_Crc(31) XOR r_Crc(28))) XOR r_Crc(22);
CrcNext(27) <= (Enable AND (Data(1) XOR r_Crc(29))) XOR r_Crc(23);
CrcNext(28) <= (Enable AND (Data(2) XOR r_Crc(30))) XOR r_Crc(24);
CrcNext(29) <= (Enable AND (Data(3) XOR r_Crc(31))) XOR r_Crc(25);
CrcNext(30) <= r_Crc(26);
CrcNext(31) <= r_Crc(27);
--CrcError <= r_Crc(31 DOWNTO 0) != x"c704dd7b"; -- CRC not equal to magic
number
p_CrcError : PROCESS (r_Crc)
BEGIN
IF r_Crc(31 DOWNTO 0) = x"c704dd7b" THEN
CrcError <= '0';
ELSE
CrcError <= '1';
END IF;
END PROCESS p_CrcError;
END flow;
-----Original Message-----
From: owner-cores@opencores.org@ROCKWELLCOLLINS On Behalf Of
deepak_1980_r@hotmail.com
Sent: Tuesday, April 29, 2003 11:57 AM
To: cores@opencores.org
Subject: [oc] Ethernet crc32 VHDL anyone?
Hi!
I'm currently working on design of 10/100Mb Ethernet MAC and
need
some quick help. Can anyone direct me to relevant vhdl code
(or
schematic design) for implementing the crc32 check.
Data will be input to the entity in 4 bit nibbles (as MII
describes).
I've been searching the web and books and seem to get
different info on
what poly is used etc.
I'm an absolute beginner so i'm having difficulty trying to
work it out the
math for myself and appreciate and help or direction. I'm
also short on
time and need to get this working within a week or so.
Thanking you
Deepak
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