RE: [oc] PID controller in FPGA?

["Renaux Jacky" <renaux.jacky@wanadoo.fr>]

Hi I think distributed arithmetic is well suited
you get 4 inputs with general LUT implementation
You have to go in deep into the z transform to find
out the final equation (and coefficients)
Using distributed arithmetic you will avoid
multiplications this one is working very well as
such is a slow process ( the DA arithmetic is
running clock speed / bits number) )

PID output = Ep*kp + Ed*kd + Ei*ki
Tn = timing sample ( the system frequency ) Ts = scaling time (system to
real ratio)
If E is error ( PID input – PID output ) En is present sample and E(n-1)
previous sample
P as proportional : obviously it is the easy part to design you’all have the
error input and load
into a shift register ( Parallel to serial register or psr) and feed on
distributed arithmetic table table
Ep = En * tn/ts
Ed as derivative
Option 1 : Ed =(En-E(n-1) )*(Tn/ts)
Option 2:  Ed= ((En-E(n-3))+ 3*(E(n-1)-E(n-2))) * (tn/ts)
Ei as integral
Ei = En + E(n-1) * tn/ts

PID = (En * k’p + (((En-E(n-3))+ 3*(E(n-1)-E(n-2))))* kd + (En +
E(n-1))*ki)*(tn/ts)
PID = (En * k’p + (((En-E(n-3))+ 3*(E(n-1)-E(n-2))))* k’d + (En + E(n-1))*k’
i)
   With k’p = kp * tn/ts , k’d = kd * tn/ts and k’i = ki * tn/ts


Potential problems

The derivative is giving the difference between samples
this means few bits (or accuracy) and then the coefficients
must be quite high

Integral : as it is a cumulative process Ed is quite large

As first results : integral will provide the number
of bits size (shift register and speed) while derivative ,
the number of bits coefficients (table size)

for distributed arith I will suggest you visit
Ray Andraka     see www.andraka.com

I hope this would help


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-----Message d'origine-----
De : owner-cores@opencores.org [mailto:owner-cores@opencores.org]De la
part de jwen@canada.com
Envoyé : jeudi 1 mai 2003 1828
À : cores@opencores.org
Objet : [oc] PID controller in FPGA?


Hi all,

I'm interested in any suggestions or information on implementing a PID
controller in an FPGA.  This should be possible without the use of a
processor.  I know there is a way to do the integration using a
summation, but what about the differentiation?

Any assistance is appreciated.

Thanks!
Jerrold.
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