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[oc] wishbone performance
From
: paul <paulw@mmail.ath.cx>
Re: [oc] Delay and latency ?
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Delay and latency ?
From
: "Jim Dempsey" <tapedisk@ameritech.net>
Re: [oc] VHDL Help...
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
[oc] Delay and latency ?
From
: "saumil merchant" <msaumil@hotmail.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave
From
: Richard Herveille <richard@asics.ws>
[oc] New available invented products
From
: dima@mail.apol.com.tw
Re: [oc] K68
From
: "Shawn Tan" <shawn.tan@aeste.net>
Re: [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave
From
: alan_m_carrspamno@yahoo.com
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Newbie question - matricies and vectors for physics
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Marko Mlinar <markom@opencores.org>
[oc] perlilog
From
: paul <paulw@mmail.ath.cx>
[oc] (No Subject)
From
: "faradhini yuniar sabara" <faradhini@eudoramail.com>
Re: [oc] Newbie question - matricies and vectors for physics
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave
From
: j1234f@excite.com
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Newbie question - matricies and vectors for physics
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Anil Sewani <sewani@qualcorelogic.com>
Re: [oc] Newbie question - matricies and vectors for physics
From
: Lars Segerlund <lars.segerlund@comsys.se>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] Newbie question - matricies and vectors for physics
From
: Sam Hale <thestormrunner@yahoo.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] i386 legally
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
[oc] K68
From
: "Shawn Tan" <shawn.tan@aeste.net>
[oc] Common IP-core metadata standardization
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
[oc] VHDL Help...
From
: =?ISO-8859-15?B?SOljdG9yIE9y824gTWFydO1uZXo=?= <hecormar@teleco.upv.es>
Re: [oc] i386 legally
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] linux xilinx webpack programming
From
: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Re: [oc] linux xilinx webpack programming
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] linux xilinx webpack programming
From
: uwe.hartl@gmx.net
Re: [oc] i386 legally
From
: "Sudarshan" <sudarshan@globaledgesoft.com>
Re: [oc] i386 legally
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] i386 legally
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] i386 legally
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] i386 legally
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] i386 legally
From
: John Dalton <john.dalton@bigfoot.com>
[oc] i386 legally
From
: paul <paulw@mmail.ath.cx>
Re: [oc] Verilog vs VHDL vs Other
From
: Tom Hawkins <tom1@launchbird.com>
[oc] Verilog 2001 Synthesis and Accelera
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
[oc] Verilog 2001 and SystemVerilog
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] a question about Verilog coding ...
From
: "Sridhar" <nandulasridhar@indiatimes.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Dian Tresna Nugraha <diantn@yahoo.com>
[oc] a question about Verilog coding ...
From
: "henry_xb" <xxiaobin@263.net>
Re: [oc] Verilog vs VHDL vs Other
From
: Marko Mlinar <markom@opencores.org>
Re: Language war, was Re: [oc] Verilog coding style ...
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: "Todd Fleming" <todd@flemingcnc.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Language war, was Re: [oc] Verilog coding style ...
From
: Andras Ferencz <opencores@ferencz.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Nicolas Boulay <nico@seul.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Nicolas Boulay <nico@seul.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Armando Astarloa <jtpascua@bi.ehu.es>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>
[oc] Verilog vs VHDL vs Other
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>
[oc] 127Hinda Cam
From
: "" <hindalive@1wigs.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Charles Lepple <charles@motioncontrol.org>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
[oc] DDR Ram verilog code
From
: kd_apte@yahoo.com
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Armando Astarloa <jtpascua@bi.ehu.es>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Bjorn Olsson <Bjorn.Olsson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Verilog vs VHDL (Was: Re: [oc] Verilog coding style...)
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
OT: Textbook Anecdote (was Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1)
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] I want some advice of DMA controller designing
From
: linyis@163.com
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: teju-dj@attbi.com
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: "Todd Fleming" <todd@flemingcnc.com>
[oc] lack of howtos
From
: paul <paulw@mmail.ath.cx>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: paul <paulw@mmail.ath.cx>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Bjorn Olsson <Bjorn.Olsson@InformAsic.com>
Re: [oc] linux xilinx webpack programming
From
: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Quartus-II (Was: Re: [oc] Verilog coding style...)
From
: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] linux xilinx webpack programming
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] linux xilinx webpack programming
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: "Chenbo Liu" <philewar@icc.sh.cn>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] linux xilinx webpack programming
From
: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Webpack Install withe wine, was: Re: [oc] linux xilinx webpack programming
From
: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: paul <paulw@mmail.ath.cx>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] writing to files
From
: daniel.mediano@sainco.abengoa.com
[oc] writing to files
From
: leire.rubio@alumni.eps.mondragon.edu
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Bjorn Olsson <Bjorn.Olsson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=<Joachim.Strombergson@InformAsic.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] linux xilinx webpack programming
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] linux xilinx webpack programming
From
: uwe.hartl@gmx.net
Re: [oc] linux xilinx webpack programming
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] linux xilinx webpack programming
From
: uwe.hartl@gmx.net
[oc] wireless mac
From
: "cfk" <cfk@pacbell.net>
Re: [oc] linux xilinx webpack programming
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] linux xilinx webpack programming
From
: ben@ben.com
Re: [oc] linux xilinx webpack programming
From
: uwe.hartl@gmx.net
Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Newbie, first proto board
From
: xerxes@intergate.ca
Re: [oc] Newbie, first proto board
From
: xerxes@intergate.ca
Re: [oc] linux xilinx webpack programming
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] linux xilinx webpack programming
From
: uwe.hartl@gmx.net
Re: [oc] Newbie, first proto board
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: "Damjan Lampret" <lampret@opencores.org>
[oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] linux xilinx webpack programming
From
: "lee ainscough" <leeainscough@hotmail.com>
[oc] linux xilinx webpack programming
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] AVNET XPA3 CPLD Board
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] AVNET XPA3 CPLD Board
From
: Shehryar Shaheen <shehryar.shaheen@ul.ie>
Re: [oc] Inquiry
From
: <cyrano@nerim.net>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] AVNET XPA3 CPLD Board
From
: Umair Farooq Siddiqi <ufarooq.geo@yahoo.com>
Re: [oc] Inquiry
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
Re: [oc] Dallas 1-Wire Search Algorithm
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] Dallas 1-Wire Search Algorithm
From
: DirkVanAken@skynet.be
[oc] Synthesis with Memory
From
: NansonHuang@ITRI.ORG.TW
Re: [oc] Automatic Core Metrics and Documentation
From
: Niclas Hedhman <niclas@hedhman.org>
file generation (was :Re: [oc] Automatic Core Metrics and Documentation)
From
: Nicolas Boulay <nico@seul.org>
[oc] Altera Cyclone development boards -- SUMMARY
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Charles Lepple <charles@motioncontrol.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: "Jim Dempsey" <tapedisk@ameritech.net>
Re: [oc] Automatic Core Metrics and Documentation
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Miha Lampret <mlampret@opencores.org>
Re: [oc] Inquiry
From
: <cyrano@nerim.net>
Re: [oc] Patents and their applicability
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Patents and their applicability
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Patents and their applicability
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] licensing made easy (2nd try)
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] Patents and their applicability
From
: John Dalton <john.dalton@bigfoot.com>
[oc] =?GB2312?B?w+K30b+0yKvH8rXnytOjocnMxvO1xND7tKvK19Gho6E=?= 8:2:
From
: =?GB2312?B?sbG+qczGt+fOxLuvvbvB99bQ0MQ=?= <xiuyuan@itv-cn.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Graham Seaman <graham@seul.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] licensing made easy (2nd try)
From
: John Dalton <john.dalton@bigfoot.com>
RE: [oc] i want code of uart16550
From
: gvvss@rediffmail.com
Re: [oc] Automatic Core Metrics and Documentation
From
: John Dalton <john.dalton@bigfoot.com>
[oc] licensing made easy (2nd try)
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] MP3 decoder?
From
: gzy_2003@sohu.com
[oc] Newbie, first proto board
From
: "Cyrus and Kristi" <xerxes@intergate.ca>
Re: [oc] Inquiry
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Inquiry
From
: Nicolas Boulay <nico@seul.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Automatic Core Metrics and Documentation
From
: Graham Seaman <graham@seul.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Automatic Core Metrics and Documentation
From
: Graham Seaman <graham@seul.org>
Re: [oc] Automatic Core Metrics and Documentation
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Video Timing generator(RS170) interlaced in VHDL help
From
: John Kent <jekent@optushome.com.au>
Re: [oc] Automatic Core Metrics and Documentation
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] T80 cpu version 0242 released
From
: "H. Peter Anvin" <hpa@zytor.com>
[oc] Altera development boards?
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] T80 cpu version 0242 released
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] Video Timing generator(RS170) interlaced in VHDL help
From
: edwinstuff@yahoo.com
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: Re: [oc] QPSK / 8-PSK / QAM Modem.
From
: "henry_xb" <xxiaobin@263.net>
Re: [oc] T80 cpu version 0242 released
From
: "H. Peter Anvin" <hpa@zytor.com>
Re: [oc] T80 cpu version 0242 released
From
: "MikeJ" <mikej@freeuk.com>
[oc] Re: Inquiry
From
: Andreas Bombe <bombe@informatik.tu-muenchen.de>
RE: [oc] urgency
From
: sphuynh <sphuynh@micron.com>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Automatic Core Metrics and Documentation
From
: Charles Lepple <charles@motioncontrol.org>
Re: [oc] USB and VME bus
From
: Charles Lepple <charles@motioncontrol.org>
Re: [oc] Inquiry
From
: Charles Lepple <charles@motioncontrol.org>
[oc] urgency
From
: =?gb2312?B?wfUg0MQ=?= <icanfly2002@hotmail.com>
Re: [oc] Automatic Core Metrics and Documentation
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] Re: Inquiry
From
: Andreas Bombe <bombe@informatik.tu-muenchen.de>
Re: [oc] Inquiry
From
: John Kent <jekent@optushome.com.au>
[oc] Re: USB and VME bus
From
: Andreas Bombe <bombe@informatik.tu-muenchen.de>
Re: [oc] QPSK / 8-PSK / QAM Modem.
From
: "Haytham" <haythamazmi@hotmail.com>
[oc] Automatic Core Metrics and Documentation
From
: Tom Hawkins <tom1@launchbird.com>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry (Replied off List)
From
: <nico@seul.org>
[oc] QPSK / 8-PSK / QAM Modem.
From
: nissimd@aeronautics-sys.com
Re: [oc] Inquiry
From
: <cyrano@nerim.net>
Re: [oc] Inquiry
From
: <cyrano@nerim.net>
OT: Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry (Replied off List)
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] Inquiry
From
: John Kent <jekent@optushome.com.au>
[oc] USB and VME bus
From
: pom gud <pomgud@yahoo.com>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: Johan Klockars <johan@klockars.net>
Re: [oc] T80 cpu version 0242 released
From
: hpa@zytor.com
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
[oc] vhdl2verilog
From
: "sudarshan" <sudarshan@ionicmicro.com>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] QAM DEMODULATOR
From
: filippo.tigli@tecnicomsrl.it
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: <nico@seul.org>
Re: [oc] Inquiry
From
: Colin Marquardt <c.marquardt@alcatel.de>
[oc] Voting [WAS: Re: Inquiry]
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] square circuts
From
: haoguang.guo@philips.com
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] square circuts
From
: John Sheahan <jrsheahan@optushome.com.au>
re: [oc] square circuts
From
: lin.sheng@zte.com.cn
Re: [oc] Inquiry
From
: Marko Mlinar <markom@opencores.org>
[oc] licensing made easy
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
[oc] square circuts
From
: haoguang.guo@philips.com
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Inquiry
From
: Billditt@aol.com
Re: [oc] Inquiry
From
: sdb@cloud9.net (Stuart Brorson)
Re: [oc] Inquiry
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: sdb@cloud9.net (Stuart Brorson)
[oc] Sonics Inc misleadin posting
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: "Damjan Lampret" <lampret@opencores.org>
Re: [oc] Inquiry
From
: Richard Herveille <richard@asics.ws>
Re: [oc] Inquiry
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] Inquiry
From
: sdb@cloud9.net (Stuart Brorson)
Re: [oc] Inquiry
From
: <cyrano@nerim.net>
Re: [oc] Inquiry
From
: Niclas Hedhman <niclas@hedhman.org>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: <nicO@seul.org>
Re: [oc] Inquiry
From
: Colin Marquardt <c.marquardt@alcatel.de>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: John Sheahan <jrsheahan@optushome.com.au>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] RAM memory
From
: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
[oc] RAM memory
From
: leire.rubio@alumni.eps.mondragon.edu
Re: [oc] Inquiry
From
: Marko Mlinar <markom@opencores.org>
Re: [oc] Inquiry
From
: "niclas" <niclas@hedhman.org>
Re: [oc] PID controller in FPGA?
From
: "niclas" <niclas@hedhman.org>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: sdb@cloud9.net (Stuart Brorson)
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] Inquiry
From
: sdb@cloud9.net (Stuart Brorson)
Re: Re: [oc] ARM Core
From
: nissimd@aeronautics-sys.com
[oc] how to express the phase in digital circut?
From
: "henry_xb" <xxiaobin@263.net>
Re: [oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Inquiry
From
: John Dalton <john.dalton@bigfoot.com>
[oc] Inquiry
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] VHDL Designers are needed
From
: konstantinos_aris@hotmail.com
RE: [oc] PID controller in FPGA?
From
: "Renaux Jacky" <renaux.jacky@wanadoo.fr>
Re: [oc] PID controller in FPGA?
From
: Charles Lepple <clepple@ghz.cc>
[oc] PID controller in FPGA?
From
: jwen@canada.com
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