Re: [oc] RAM memory

[Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>]

Aloha!

leire.rubio@alumni.eps.mondragon.edu wrote:
> Hello! 
> I would like to create a RAM to save incoming serial data and work with 
> it. I know that a CLB has LUTs that in my opinion are the best way to 
> implement memory. But how could we do a VHDL design that uses them 
> and not other logic?
> Thanks in advance, Leire

Since you talk about CLBs and LUTs I venture a guess that you are using Xilinx 
FPGAs as target technology, correct? In that case, there are tons of great 
examples and help on the Xilinx web page, these for example:

http://search.xilinx.com/search97cgi/s97r_cgi

Also, remember Google is your friend:
http://www.google.com/search?hl=en&lr=&ie=UTF-8&q=How+to+instantiate+a+memory+array+in+VHDL+Xilinx+FPGA&spell=1

Good luck!

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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