Re: [oc] T80 cpu version 0242 released

["H. Peter Anvin" <hpa@zytor.com>]

MikeJ wrote:
> Hi,
> 
> It is a right pain to use a mixture of positive and negative edge clocking,
> so if possible use a clock that is twice the frequency instead. The T80 core
> bus timing has been simplified for this reason, but if you need 2 clock r/w
> cycles then have a look at the T80 core in the Pacman code which uses the
> t80sed (synchronous, clock enable, double cycle) module to do this.
> 

That's pretty much what I've found as well -- my "correct" clocking 
module works great in simulation, but for synthesis it seems to generate 
completely non-functional crap.  I'm going to try to change it to a 
double-rate clock later today and see if it works better.

What I'm trying to do is to get a 25 MHz T80 model to operate together 
with a 100 MHz SDRAM (actually 133 MHz, but clocked at 100 MHz) without 
incurring wait states.  At least for the part I'm using, the total cycle 
time tRC = 7 clocks, so equal to 1.75 CPU cycles.  However, the data 
becomes available after 4 clocks, 1.0 CPU cycles -- however, that's 
assuming that everything is set up to issue the RA command at the rising 
edge of the very first cycle.  This means the change from 1.5 cycles 
(Z80 timing) to 1.0 cycles (T80 timing) means there isn't time to do 
this anymore, and I'd like to avoid adding wait states if I can.  If I 
can't -- i.e. a "true Z80" timing model no longer meets timing for 
synthesis at 25 MHz -- then that's another thing, of course.

I'll try my own module first, but if it doesn't work then I'll try the 
T80sed module.

    -hpa
    ...who is starting to desperately wish VHLD had #include and #ifdef

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