Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[John Sheahan <jrsheahan@optushome.com.au>]

On Tue, May 20, 2003 at 12:35:26AM +0700, Rudolf Usselmann wrote:
> There is no
> QA, or even such basic things as verification at OC. Designers
> verify their own cores ! This is horrible in my opinion. You know
> the chances that you will duplicate a bug in the test bench that
> you did in your RTL are very great. So why even bother ?!

good point. 
perhaps part of the core summary discussed earlier should  
include  (someone) rating the scope of the testbench, 
and perhaps flag when the TB is mostly the work of the core designer.

Having someonen else extend and exercise the TB is usually a 
great way of improving quality. 

Then there is the quality/relevance of the comments. 

For me, clean consistant code, well commented with good testbenches 
outweighs  conformance with any particular style.   

john
  
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml