Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[John Sheahan <jrsheahan@optushome.com.au>]

On Tue, May 20, 2003 at 01:28:44PM -0300, Marco Antonio Simon Dal Poz wrote:
> 
> Ok, I forgot to tell I was talking about FPGAs. I hadn't imagine that ASIC
> market was that different from FPGA market.

its very different. there are a number of reasons when you think about
it.

> 
> What is the big deal with Synopsys tools that it has been chosen as THE
> tools and not Cadence and MG tools?

Synopsis created design compiler at the right time. Most of their
tools continue to do a good job.  Most ASIC people would  like to
see competition to Synopsys so its not a single-master market, and so
the tools continue to improve.


> > One area *not* dominated by Synopsys is FPGAs. But it's a pretty slim market 
> > in terms of money, and the free tool offerings from Xilinx and Altera are 
> > eating away the margins from below.
> 
> I don't think the problem is the margins.

medium/longer term it is. Altera/Xilinx make money selling silicon. 
The tools enable/enhance the silicon sales.  
Synopsys + cadence + +mentor (without leonardo/Modelsim) are more
tools based. I think the fpga companies lag in good tool development.   

> 
> I am used to do FPGA hardware design with Verilog and VHDL, and I can't
> see why Verilog is so better than VHDL. In fact, I see advantages and
> disadvantages in both sides, so, why Verilog is still dominant?

this is a fair statement. For big things, verilog is dominant for
historical reasons, and I _personally_ like it more. Whats wrong with several
languages?  We still have multiple religions.

john
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