Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>]

Aloha!

First: VHDL is first and foremost a simulation market in which a subset can be 
used for RTL description and can thus be synthesised (down to a GTL in Verilog 
;-).

Verilog lacks quite a few of the nice, abstraction features that makes VHDL a 
good behavioural modelling and simulation tool. Verilog OTOH is a smaller and 
simpler language mainly geared for RTL and GTL implementation.

Some of the deficits in terms of modelling, data structures was very nicely 
added in Superlog, which is now turning into SystemVerilog. Additionally 
SystemVerilog adds good verification features such as assertions etc.

Armando Astarloa wrote:
> but for investigation purposes VHDL is 
> used widely (see for example POLIS team [TABB00]    B. Tabbara,  A. 
> Tabbara,  A. Sangiovanni-Vicentelli, Function / Architecture 
> Optimization and Co-Design of Embedded Systems, Massachusetts, USA:  
> Kluwer Academic Publishers, 2000. ).

Yes, VHDL is widely used, but in terms of market share it is dwarfed by 
Verilog. A coiple of examples:

The total market according to SNUG2002 looked like this (Verilog vs VHDL) 
(Source: http://www.deepchip.com/posts/snug02.html):

<snip>
GONE COMMODITY:  From the Dataquest 2000 market share numbers and reader
response, Synopsys VCS and Cadence NC-Verilog each own about half of their
market.  ModelTech owns 73% of the mixed Verilog/VHDL simulation market
and nobody really cares about pure VHDL simulators like Scirroco any more.

     Dataquest FY 2000 Simulator Markets (in $ Millions)

      Verilog Total  ######################################## $120.7

           Synopsys  ################## $55.5 (46%)
            Cadence  ################## $53.1 (44%)
         Fintronics  ## $7.2 (6%)
             others  ## $4.8 (4%)

       Verilog/VHDL
    Mixed Sim Total  ############################ $85.2

          ModelTech  ##################### $62.2 (73%)
            Cadence  ####### $21.3 (25%)
             others  # $1.7 (2%)

         VHDL Total  ####### $22.1

            Cadence  #### $10.8 (49%)
              Aldec  ## $6.6 (30%)
           Synopsys  # $4.0 (18%)
             others  $0.7 (3%)

The other thing to notice in this data is that 52.9% of designers do pure
Verilog design, while only 9.6% do pure VHDL.  The remaining 37.4% have
their feet in both Verilog/VHDL worlds probably because of 3rd party IP.
</snip>

This is only the simulation market, but since it's mainly RTL-level it gives a 
good indication on the usage of Verilog vs VHDL for design implementation.

> I dont agree that Verilog is dominant everywhere. 100% of the companies 
> and Universities in my area uses VHDL. There are no Verilog seminars and 
> all the tools that the EDA vendors offer are for VHDL design.

Which planet do you live on? ;-)

In academia I see basically only VHDL. In industry, especially smaller 
companies doing FPGAs quite a few (I would even say most of them) in Sweden 
use VHDL. But VHDL only tools? Which ones? Synopsys? Cadence? Mentor? Magma? 
Synplicity?

These vendors all offer either both Verilog and VHDL *or* Verilog only. I know 
of one or two smaller, European based EDA-companies (spin off from academia) 
that started with VHDL. But the ones I know about are developing Verilog 
support now. Why? Look at the numbers, that's where the money is.

Also about Europe vs USA. Europe is not 100% VHDL or anything. There are huge 
number of designs done in Verilog here too. Esp for telecom (switching) and 
datacom - and more ASICs that FPGAs. I wouldn't even bet that VHDL by sheer 
numbers is more common in the European industry than Verilog.

VHDL might very well dominate in academia, but there is no money to be made in 
academia for the EDA vendors. It's the industry that counts. The biggest 
EDA-market is the US followed by Asia. The US and Asia are Verilog markets.

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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