Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Dian Tresna Nugraha <diantn@yahoo.com>]

> I use verilog because 99.5% of my customers ask for verilog
> support/solutions. I bought VHDL books twice to learn VHDL,
> ended up throwing/giving both away, never learning VHDL. :*(
> 
> Regards, 
> rudi               

If we really want, trying to port one of the available Verilog-core into VHDL (or vice-versa) with
the same level of quality will give us experience of both languages. 

As designers, our concern should be more to the hardware itself. The choice of a language is just
like we choose English or French in a conversation ( or to serve a customer like in Rudi's case).
In my opinion, both of the language can describe well what we need to describe a digital
microelectronic circuit. The availability of synthesis tool for both language proves us that the
two language are qualified for our needs.

Moreover, they are now provided with Analog and Mixed-Signal extension. I would really like to
know which Verilog or VHDL can / can't describe, that has big affect to our design. Then after
this, we might consider to build a new language specification (like SystemC or UML perhaps).

Wise EDA tools vendor should give freedom to the designer's taste of choosing language, either
Verilog or VHDL. And modules written in both language should be able to run in a
co-simulation/verification. Like one software company frees us to choose C++, C#, Java, VB, or
whatever in its platform. Our imagination and ideas are more important.

So, lets feel free to 'speak' out our microelectronic device. 
It's the job of synthesis tool to generate it.

^_^

Dian.

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